The following command translates your design to a Verilog file.
ngd2ver [options] infile[.ngd|.nga] [outfile[.v]]
Options can be any number of the NGD2VER options listed in the “NGD2VER Options” section. They do not need to be listed in any particular order. Separate multiple options with spaces.
Infile [.ngd|.nga] is the input NGD or NGA file. If you enter a file name with no extension, NGD2VER looks for a file with an .nga extension and the name you specified. If you want to translate an NGD file, you must enter the .ngd extension. Without the .ngd extension NGD2VER does not use the NGD file as input, even if an NGA file is not present.
Outfile[.v] indicates the file to which the Verilog output of NGD2VER is written. Default is infile.v (infile is the same root name as the input file). The SDF file has the same root name as the Verilog file.
