This section describes NGD2VER command options.
The -aka option includes user-defined identifiers as comments in the Verilog netlist. This option is used if user-defined identifiers are changed because of name legalization processes in NGD2VER.
The -cd option applies to a Verilog file that will be used with the Cadence Synergy synthesis tool. The -cd option encloses every module definition in `celldefine and `endcelldefine constructs, as shown below.
`celldefine
module <module_name>
.
.
.
endmodule
`endcelldefine
The `celldefine and `endcelldefine constructs tell the Cadence Synergy software to treat an enclosed module as a black box (that is, do not try to synthesize the enclosed module).
This option is used if a Cadence Synergy user instantiates a LogiBLOX module into the HDL source code.
-f command_file
The -f option executes the command line arguments in the specified command_file. For more information on the -f option, see the “-f Option” section of the “Introduction” chapter.
-gp port_name
The -gp option causes NGD2VER to bring out the global reset signal (which is connected to all flip-flops and latches in the physical design) as a port on the top-level module in the output Verilog file. Specifying the port name allows you to match the port name you used in the front-end. The global reset signal is discussed in the “Dedicated Global Signals in Back-Annotation Simulation” section of the “NGDAnno” chapter.
This option is only used if the global reset net is not driven. For example, if you include a STARTUP component in an XC4000 design, you do not have to enter a -gp option, because the STARTUP component drives the global reset net.
Do not use GR, GSR, PRELOAD, or RESET as port names, because these are reserved names in the Xilinx software.
-log log_file
The -log option generates a log file that contains all of the messages displayed during the execution of NGD2VER. Specify the name of the log file. By default, the name is ngd2ver.log.
The -ne option overrides the default NGD2VER method of writing out identifiers with invalid characters.
In a Verilog file, identifiers (names) must conform to the following rules.
By default (with no -ne option), NGD2VER writes identifiers with invalid characters in accordance with the preceding rules (that is, with a leading backslash and a following white space).
If you enter a -ne option, invalid characters are replaced with an underscore character (_), and the leading backslash does not appear as part of the identifier. The resulting Verilog file can be used if a vendor's Verilog software cannot interpret escaped identifiers correctly.
-op oscillator_period
The -op option specifies the period, in nanoseconds, for the oscillator. You must specify a positive integer to stimulate the component properly. If you do not enter a value for the -op option, the default is 100 ns.
The -pf option writes out a pin file - a Cadence signal-to-pin mapping file with a .pin extension.
The -pms option forces the port names and child signal names to match.
The -r option writes out a Verilog HDL file that retains the hierarchy in the original design. The default setting (with no -r option) produces a flattened Verilog HDL file.
The option groups logic based on the original design hierarchy. To run NGD2VER with the -r option, you must have supplied an NGM file as input when you ran NGDANNO (see the “Input Files” section of the “NGDAnno” chapter).
-sdf_path [path_name]
The -sdf option outputs the SDF file to the specified full path. This option writes the full path and the SDF file name to the $sdf_annotate statement. If a full path is not specified, it writes the full path of the current work directory and the SDF file name to the $sdf_annotate file.
The -shm option places $shm statements in the structural Verilog file created by NGD2VER. These $shm statements allow VerilogXL to display simulation data as waveforms.
The -tf option generates a test fixture file. The file has a .tv extension, and it is a ready-to-use template test fixture Verilog file based on the input NGD or NGA file.
If you are using a Cadence Verilog simulator, you can run the simulator by entering verilog design.tv design.v, using the output V and TV files from NGD2VER. You can then add more design-specific stimuli to this file to fit your needs.
-ti top_instance_name
The -ti option specifies a user instance name for the design under test in the test fixture file created with the -tf option.
-tm top_module_name
The -tm option changes the name of the top-level module name appearing within the NGD2VER output files. If you do not enter a -tm option, the output files inherit the top module name from the input NGD or NGA file.
-tp port_name
The -tp option causes NGD2VER to bring out the global tristate signal (which forces all FPGA outputs to the high-impedance state) as a port on the top-level entity in the output Verilog file. Specifying the port name allows you to match the port name you used in the front-end.
This option is only used if the global tristate net is not driven. For example, if you include a STARTUP component in an XC4000 design, you do not have to enter a -tp option, because the STARTUP component drives the global tristate net.
The -u option produces an output Verilog file compatible with an AT&T Verilog simulator. This file contains an underbar (_) as a path delimiter, instead of the default forward slash (/) that is compatible with a Cadence Verilog simulator.
The -ul option causes NGD2VER to write a library path pointing to the SIMPRIM library into the output Verilog (.v) file. The path is written as shown following.
`uselib dir=$XILINX/verilog/data libext=.vmd
$XILINX is the location of the Xilinx software.
This line is necessary for a Cadence Verilog simulator, but may confuse a simulator from another vendor. If you do not enter a -ul option, the `uselib line is not written into the Verilog file.
The -verbose option displays detailed Verilog processing messages during the execution of NGD2VER.
The -w option causes NGD2VER to overwrite the output files if they already exist. By default (no -w specified) NGD2VER does not overwrite existing files.
