At the beginning of an FPGA design simulation, you must toggle the global set/reset signal (GSR in XC4000E/L/EX/XL/XV/XLA, Spartan, SpartanXL, or Virtex designs) or the global reset signal (GR in XC5200, XC3000A/L, or XC3100A/L designs). Toggling the global set/reset emulates the power-on reset of the FPGA. If you do not do this, the flip-flops and latches in your simulation may not function correctly.
The global set/reset net is present in your implemented design even if you do not instantiate the STARTUP block in your design. The function of STARTUP is to give you the option to control the global reset net from an external pin.
The term “STARTUP” refers to the STARTUP block for all device families, including the Virtex STARTUP block, STARTUP_VIRTEX. STARTUP_VIRTEX is a subset of the XC4000 STARTUP block. It differs from the XC4000 STARTUP block in that is has no outputs, as shown in the following figure.
Figure 17.2 STARTUP and STARTUP_VIRTEX Blocks |  |
If you want to select the global set/reset pulse width so that it reflects the actual amount of time it takes for the chip to go through the reset process when power is supplied to it, refer to The Programmable Logic Data Book for the device you are simulating.
The general procedure for specifying global set/reset or global reset during a pre-NGDBuild Verilog UNISIM simulation involves defining the global reset signals with one of the following Verilog macros: GSR_SIGNAL or GR_SIGNAL. This is necessary because these global nets do not exist in the UNISIM libraries, and as a result, the reset of the UNISIM components is controlled by the detection of the GSR_SIGNAL or GR_SIGNAL macros. In addition, you must declare the global set/reset signal either as a Verilog wire or reg. Your choice of wire or reg depends on if your design contains a STARTUP component.
In the Xilinx software, the Verilog UNISIM library is only used in RTL simulations of your designs. Simulation at other points in the flow use the Verilog SIMPRIM Libraries. This occurs because the FPGA Compiler writes out unexpanded LogiBLOX type modules that do not have corresponding models. However, there are models for VHDL that VSS can use.
For pre-NGDBuild UNISIM functional simulation, you must set the value of the appropriate Verilog macro (GSR_SIGNAL or GR_SIGNAL) to the name of the GSR or GR net, qualified by the appropriate scope identifiers.
GSR_SIGNAL and GR_SIGNAL are used in the Verilog UNISIM to emulate the global reset signals.
The scope identifiers are a combination of the test module scope and the design instance scope. The scope qualifiers are required because the scope information is needed when the GSR_SIGNAL and GR_SIGNAL macros are interpreted by the Verilog UNISIM simulation models to emulate a global reset signal.
The net name you specify, and whether you specify the net as a Verilog reg or a wire, depends on if your design includes an instantiated STARTBUF.
The term “STARTBUF” refers to the STARTBUF cell for all device families, including the Virtex STARTBUF cell, STARTBUF_VIRTEX. STARTBUF_VIRTEX is similar to the STARTBUF, but GSROUT is not available.
Use the following steps to define the global set/reset signals in a test fixture file for your design.
Use the first step if you do not have a STARTBUF in your design, otherwise proceed to the second step.
Test refers to the test fixture module name and design_instance refers to the designated instance name for the instantiated design netlist within the test fixture file.
For Unified Library functional simulation, you must always define the appropriate Verilog macro (GSR_SIGNAL or GR_SIGNAL) for the global set/reset signal. (This macro is not used in timing simulation when there is a STARTUP block in your design.)
The GSR signal in XC4000E/L/EX/XL/XV/XLA, Spartan, SpartanXL, and Virtex devices and the GR signal in XC5200 devices is active-High, and the GR signal in XC3000A/L and XC3100A/L devices is active-Low.
For post-NGDBuild and post-route timing simulation, the test fixture template (TV file) produced by running NGD2VER with the -tf option contains most of the code previously described for defining and toggling GSR or GR. However, if you use a signal to control the STARTUP block, you must manually edit the test fixture template file (generated by NGD2VER) to specify the signal connected to the GSR or GR pin on the STARTUP block symbol as GSR_SIGNAL (XC4000, Spartan, Virtex families) or GR_SIGNAL (XC5200).
If you do not have a STARTUP block in your design, you can use the same test fixture file with little or no modification at all stages of the design flow, as described in the following examples.
The following design shows how to drive the GSR signal in a Verilog-XL test fixture file at the beginning of a pre-NGDBuild Unified Library functional simulation.
Reference the global set/reset net as GSR in XC4000E/L/EX/XL/XV/XLA, Spartan, SpartanXL, or Virtex designs without a STARTUP block. The Verilog macro defining the global net must be referenced as GSR_SIGNAL because this is how it is modeled in the Verilog UNISIM library.
In the design code, declare GSR as a Verilog wire; however, it is not specified in the port list for the module.
Describe GSR to reset or preset every inferred register or latch in your design. GSR does not need to be connected to any instantiated registers or latches, as shown in the following example.
module my_counter (CLOCK, COUT, Q, D);
input CLOCK, D;
output Q;
output [3:0] COUT;
wire GSR;
always @(posedge GSR or posedge CLOCK)
begin
if (GSR == 1'b1)
COUT = 4'h0;
else
COUT = COUT + 1'b1;
end
// Example of an instantiated FDCE
//
// If a macro name GSR_SIGNAL is defined in the
// testbench, CLR does not need to be connected
// to GSR and flop will still be reset with GSR.
FDCE test_flop (.Q(Q), .D (D), .C(CLOCK),
.CE (open), .CLR (open));
endmoduleBecause GSR is declared as a floating wire and is not in the port list, the synthesis tool optimizes the GSR signal out of the design. GSR is replaced later by the implementation software for all post-implementation simulation netlists.
In the test fixture file, set a GSR_SIGNAL macro to test.my_counter.GSR (the name of the global set/reset signal, qualified by the name of the design instantiation instance name and the test fixture module name) using the `define compiler directive, as follows.
`define GSR_SIGNAL test.my_counter.GSR
GSR_SIGNAL should be toggled High, then Low at the beginning of an initial block using the force command.
module test;
`define GSR_SIGNAL test.my_counter.GSR
count4 my_counter (.CLOCK (CLOCK), .COUT(COUT), .Q(Q), .D(D));
reg CLOCK, D;
initial
begin
CLOCK = 0;
D = 0;
force `GSR_SIGNAL = 1; //Here is the Global Reset
#100 force `GSR_SIGNAL = 0; //End of Global Reset
//rest of simulation stimuli
end
endmoduleIn this example, the active-High GSR signal in the XC4000 family device is activated by driving it High. 100ns later, it is deactivated by driving it Low. (100ns is an arbitrarily chosen value.)
You can use the same test fixture for simulating at other stages in the design flow if this methodology is used.
For pre-NGDBuild functional simulation, the active-High GR net in XC5200 devices should be simulated in the same manner as GSR for XC4000E/L/EX/XL/XV/XLA, Spartan, SpartanXL, and Virtex.
In the design code, GR should be declared as a Verilog wire and not specified in the port list for the module. GR should be described to reset every inferred register or latch in the design. GR does not need to be connected to any instantiated registers or latches.
module my_counter (CLOCK, COUT, Q, D);
input CLOCK, D;
output Q;
output [3:0] COUT;
wire GR;
always @(posedge GR or posedge CLOCK)
begin
if (GR == 1'b1)
COUT = 4'h0;
else
COUT = COUT + 1'b1;
end
// Example of an instantiated FDCE
//
// If a macro name GR_SIGNAL is defined in the
// testbench, CLR does not need to be connected
// to GR and flop will still be reset with GR.
FDCE test_flop (.Q(Q), .D (D), .C(CLOCK),
.CE (open), .CLR (open));
endmoduleIn the test fixture file, set a macro called GR_SIGNAL to test.my_counter.GR (the name of the global set/reset signal, qualified by the name of the design instantiation instance name and the test fixture module name) using the `define compiler directive, as follows.
`define GR_SIGNAL test.my_counter.GR
GR_SIGNAL should be toggled High, then Low at the beginning of an initial block using the force command.
module test;
`define GR_SIGNAL test.my_counter.GR
count4 my_counter (.CLOCK (CLOCK), .COUT(COUT), .Q(Q), .D(D));
reg CLOCK, D;
initial
begin
CLOCK = 0;
D = 0;
force `GR_SIGNAL = 1; //Here is the Global Reset
#100 force `GR_SIGNAL = 0; //End of Global Reset
//rest of simulation stimuli
end
endmoduleIn this example, the active-High GR signal in the XC5200 family device is activated by driving it High. 100ns later, it is deactivated by driving it Low. (100ns is an arbitrarily chosen value.)
You can use the same test fixture for simulating at other stages of the design if this methodology is used.
Asserting global reset in XC3000A/L and XC3100A/L designs is almost identical to the procedure for asserting global reset in XC5200 designs, except that GR in XC3000A/L and XC3100A/L devices is active-Low. (Also note that the STARTUP block is not supported on XC3000A/L and XC3100A/L devices).
module test;
reg GR;
`define GR_SIGNAL test.GR;
initial
begin
`GR_SIGNAL = 0;// reset the device
#100 `GR_SIGNAL = 1;The Global Reset (GR) signal in the XC3000A/L architecture is modeled differently in functional simulation netlists and SIMPRIM library-based netlists generated by NGD2VER. In the Verilog Unified Library, GR is modeled as a wire within a global module, while in a SIMPRIM-based netlist, it is always modeled as an external port. As a result, you cannot use the same test fixture file for both Unified library simulation and SIMPRIM-based simulation.
Asserting global set/reset when the STARTUP block is specified in your design is similar to asserting global set/reset without a STARTUP block in your design. However, there are the following two differences.
`define GSR_SIGNAL net_connected_to_GSR_pininitial
begin
GSR_user_control_signal = 0;
#100 GSR_user_control_signal = 1;Figure 17.3 Verilog User-Controlled Inverted GSR | |
The STARTUP_VIRTEX block differs slightly in that is has no outputs.
The following is an example of driving the global set/reset signal in a test fixture file at the beginning of an RTL or post-synthesis functional simulation when there is a STARTUP block in an XC4000E/L/EX/XL/XV/XLA, Spartan, SpartanXL, or Virtex design.
In the following figure, the mygsr signal is the GSR_user_control_signal. In this case, mygsr is an external user signal that controls GSR. Mygsr sources an IBUF, which in turn sources the gsrin signal. Gsrin represents the net_connected_to_GSR_pin pin that directly sources the GSR pin of the STARTUP block.
Figure 17.4 Verilog User-Controlled GSR | |
The STARTUP_VIRTEX block differs slightly in that is has no outputs.
This design allows you to control global set/reset in the device by driving the external mygsr input port. ;In the test fixture file, mygsr is a Verilog reg in the test module.
module test;
reg mygsr;In addition, for XC4000E/L/EX/XL/XV/XLA, Spartan, SpartanXL, and Virtex designs, a Verilog macro called GSR_SIGNAL must be declared to make the connection between the user logic and the global GSR net embedded in the Unified Library models. This is done by using a `define directive to set GSR_SIGNAL to the following.
test_module_name.design_instance_name.gsr_pin_signalGsr_pin_signal corresponds to the name of the signal connected to the GSR pin on the STARTUP block (in this case, gsrin). The scope qualifier in this case also includes the name of the design instance (uut) in anticipation that the net appears as an internal net of the design in the post-NGDBuild, post-Map, and post-route simulations further in the design flow.
The global set/reset control signal should be toggled High, then Low in an initial block.
module test;
reg mygsr;
`define GSR_SIGNAL test.uut.gsrin;initial
begin
mygsr = 1;// reset the device
#100 mygsr = 0;For post-NGDBuild functional simulation, post-Map timing simulation, and post-route timing simulation, the procedure is identical to Unified Library functional simulation, except that you must omit the `define statement for GSR_SIGNAL. This is done because the net connections exist in the post-NGDBuild design, and retaining the macro definition causes a possible conflict with these connections. In the following example, the macro definition is commented out to avoid a possible conflict.
module test;
reg mygsr;
// `define GSR_SIGNAL test.uut.gsrin;
initial
begin
mygsr = 1;// reset the device
#100 mygsr = 0;For a XC5200 design with a STARTUP block, the net controlling GR should be stimulated in the same manner as for the XC4000E/L/EX/XL/XV/XLA.
Substitute GR_SIGNAL for GSR_SIGNAL, mygr for mygsr, and gr_in for gsr_in in “Example 1a: XC4000E/L/EX/XL/XV/XLA, Spartan, SpartanXL, and Virtex RTL and Post-synthesis Simulation (With STARTUP)” to obtain the test fixture fragment for stimulating GR in a Verilog RTL or post-synthesis simulation.
Figure 17.5 Verilog User-Controlled Inverted GR | |
module test;
reg mygr;
`define GR_SIGNAL test.uut.gr_in;
initial
begin
mygr = 1;// reset the device
#100 mygr = 0;For post-NGDBuild functional simulation, post-Map timing simulation, and post-route timing simulation, the procedure is identical to Unified Library functional simulation, except that you must omit the `define statement for GR_SIGNAL. This is done because the net connections exist in the post-NGDBuild design, and retaining the macro definition may cause a conflict with these connections. In the following example the Verilog macro definition is commented out to avoid a possible conflict.
module test;
reg mygr;
// `define GR_SIGNAL test.uut.gr_in;
initial
begin
mygr = 1;// reset the device
#100 mygr = 0;STARTUP is not supported or required in XC3000A/L and XC3100A/L designs. Follow the procedure for XC3000A/L and XC3100A/L designs without STARTUP blocks.
