Creating a Design for Use with the Hardware Debugger

To create a design that you can use with the Hardware Debugger, follow the design generation instructions for the type of operation you want to complete for your specific device.

Preparing a Downloadable Design

When using the Hardware Debugger to download a design only, you do not need any special symbols in the design. Leave all options at their default values.

Preparing a Design for Verification and Debugging

Readback is the process of reading a bitstream from an FPGA. The bitstream contains configuration information and information about the state of the design. You can use the readback bitstream to verify the configuration and probe the internal states of your design.

Preparing an XC3000 Design for Verification and Debugging

An XC3000 design does not need to be modified at the schematic or HDL level in order to perform readback. For XC3000 devices, a readback is initiated when a Low to High transition is applied to the M0/RTRIG pin. After the readback begins, the serial readback data is presented on the M1(RDATA) pin.

Preparing XC4000/XC5200 Designs for Verification and Debugging

To provide more flexibility, the XC4000/XC5200 readback signals (RTRIG and RDATA) can be assigned to any of the user programmable device pins as well as the M0 and M1 pins. Because the readback signals are user programmable, you must use the READBACK component in the design when using the Hardware Debugger to verify or debug an XC4000 or an XC5200 device.

To prepare the design for verifying or debugging, use the following steps.

1. Include the READBACK symbol in the design schematic.
   
   
2. Connect IPAD, OPAD, IBUF, and OBUF primitives to the TRIG and DATA pins of the READBACK macro as shown in the “READBACK Symbol” figure. You can then lock the IPAD and OPAD components to any of the user-programmable I/O locations.
   
   

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   NOTE

   If you want TRIG and DATA to correspond to the mode pins M0 and M1, replace the IPAD and OPAD primitives with the special primitives MD0 and MD1.

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   Figure 3.1 READBACK Symbol

3. If you plan to have the Hardware Debugger reset the flip-flops in the design, include the STARTUP symbol and connect the GSR (XC4000) or GR (XC5200) input pin to an unused input of the target device. You will later connect the input to the RESET pin on the XChecker cable.
   
   

NOTE

Because the XC4000/XC5200 reset is active-High and the Hardware Debugger assumes active-Low, the signal sent from the Hardware Debugger through XChecker must be inverted as shown in the “XC4000 STARTUP Symbol” figure and the “XC5200 STARTUP Symbol” figure.

Figure 3.2 XC4000 STARTUP Symbol

Figure 3.3 XC5200 STARTUP Symbol

The inverter preceding the STARTUP symbol implements the active-Low reset asserted by the Hardware Debugger.