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Generating Configuration Data Files

After you place and route the design, you must generate the configuration data files. The Hardware Debugger can download to a chain of multiple devices, known as a daisy chain, as well as to an individual device. The Hardware Debugger can only verify the configuration data and probe the internal states of a single device at a time. It is possible to verify and debug a device configured on a daisy chain only if you connect the XChecker cable directly to it. This process of probing a configured device is also known as readback.

To generate a bitstream, open the implementation revision from the Design Manager. If you do not have a project for your design, use the Design Manager to create a project for that design. If you have a project for your design but the project has not been updated, run the Design New Version command to read in the changes made in the schematic and to create a new version reflecting the updated schematic. Then, implement the design as explained in the “Implementing a Design” section of the Design Manager/Flow Engine Reference/User Guide.

For detailed information on the various implementation and configuration options, see the “Implementation Options” chapter of the Design Manager/Flow Engine Reference/User Guide.

Creating Files for a Single XC3000 Device

To configure an XC3000 device, you need a bitstream. The Hardware Debugger accepts a bitstream as a BIT file, an RBT file, or a PROM file. To verify and/or debug a design, you must use a BIT file and have a logic allocation file (design_name.ll) in your design directory. Use the Design Manager to generate these files.

Creating Downloadable Files (XC3000)

Follow these steps to prepare your XC3000 designs for downloading.

  1. From the Design Manager, click the left mouse button on the implementation revision, as shown in the “XC3000 Implementation Revision in the Design Manager” figure.

  2. Select Design Implement.

    Figure 3.4 XC3000 Implementation Revision in the Design Manager

  3. In the Implement dialog box, click the Options button.

    The Options dialog box appears, as shown in the “Design Manager Options Dialog Box” figure.

    Figure 3.5 Design Manager Options Dialog Box

  4. Select Produce Configuration Data in the Optional Targets group box.

  5. Click the Edit Template button corresponding to the configuration template.

    The Configuration Template dialog box appears, as shown in the “Design Manager Configuration Template Dialog Box” figure.

    Figure 3.6 Design Manager Configuration Template Dialog Box

  6. Select Pullup next to the Done/Program pin in the Configuration Pin Pullups group box to enable a 2 to 8 kilohm pull-up resistor on the D/P pin.

  7. Click OK to return to the Options dialog box or if you want to enable the readback options, continue with the next “Creating Files for Verification and Debugging (XC3000)” section.

  8. In the Options dialog box, click OK to return to the Implement dialog box.

  9. In the Implement dialog box, select Run to implement the design and produce the configuration data.

Creating Files for Verification and Debugging (XC3000)

Follow these steps to implement XC3000 designs for verification and debugging.

  1. Follow steps 1 through 6 in the preceding “Creating Downloadable Files (XC3000)” section to enable a pull-up resistor for the D/P pin for device configuration.

  2. Select the Startup/Readback tab of the Configuration Template dialog box. The Startup/Readback tab appears, as shown in the “Configuration Template Startup/Readback Tab” figure.

    Figure 3.7 Configuration Template Startup/Readback Tab

  3. Enable the readback capability by choosing On Command for the Readback option.

    The software generates a logic allocation file (design_name.ll). The Hardware Debugger uses the design_name.ll file to identify bits in the readback bitstream that represent the values of design I/Os, latches, and flip-flops. For more information about configuration options, read the “Implementation Options” chapter in the Design Manager/Flow Engine Reference/User Guide.

  4. Click OK in the Configuration Template dialog box to return to the Options dialog box.

  5. In the Options dialog box, click OK to return to the Implement dialog box.

  6. In the Implement dialog box, select Run to implement the design and produce the configuration data.

Creating Files for a Single XC4000 or XC5200 Device

To configure an XC4000 or XC5200 device, you need a bitstream, which can be either a BIT file, an RBT file, or a PROM file. To verify and/or debug a design, you must use a BIT file and have a logic allocation file (design_name.ll) in your design directory. Use the Design Manager to generate the necessary configuration files.

Creating Downloadable Files (XC4000/XC5200)

Follow these steps to prepare your XC4000 and XC5200 designs for downloading.

  1. From the Design Manager, click the left mouse button on the implementation revision, as shown in the “XC4000 Implementation Revision in the Design Manager” figure.

  2. Select Design Implement.

    Figure 3.8 XC4000 Implementation Revision in the Design Manager

  3. In the Implement dialog box, click Options.

    The Options dialog box appears, as shown in the “Design Manager Options Dialog Box” figure.

  4. Select Produce Configuration Data in the Optional Targets group box.

  5. Click the Edit Template button corresponding to the configuration template.

    The Configuration Template dialog box appears, as shown in the “Design Manager Configuration Template Dialog Box” figure.

    Figure 3.9 Design Manager Configuration Template Dialog Box

  6. Select PullUp next to the DONE pin in the Configuration Pins group box to enable a pull-up resistor for the DONE pin.

  7. Select Perform CRC During Configuration (default) to perform a cyclic redundancy check of your bitstream during configuration. This is optional.

    CRC bits are checksum bits that the FPGA uses to verify that the bitstream transmitted correctly.

  8. Select Produce ASCII Configuration File to create a rawbits text (RBT) file, which is an ASCII representation of your configuration bitstream. This is optional.

    You can use the RBT file for download or to visually inspect your bitstream.

  9. Click OK to return to the Options dialog box or if you want to enable the readback options, continue with the next “Creating Files for Verification and Debugging (XC4000/XC5200)” section.

  10. In the Options dialog box, click OK to return to the Implement dialog box.

  11. In the Implement dialog box, select Run to compile the design and produce the configuration data.

  12. To obtain help, click Help in the dialog box.

Creating Files for Verification and Debugging (XC4000/XC5200)

Follow these steps to implement XC4000 and XC5200 designs for verification and debugging.

  1. Follow steps 1 through 6 in the preceding “Creating Downloadable Files (XC4000/XC5200)” section to enable a pull-up resistor for the D/P pin for device configuration.

  2. In the Configuration Template dialog box, select the Readback tab. The Readback tab of the Configuration Template dialog box appears, as shown in the “Configuration Template Readback Tab” figure.

  3. Select CCLK as the readback clock.

    Figure 3.10 Configuration Template Readback Tab

  4. Select Enable Bitstream Verification and In-Circuit Hardware Debugging.

    This option generates the logic allocation file (design_name.ll). The Hardware Debugger uses the design_name.ll file to identify bits in the readback bitstream that represent the values of design I/Os, latches, and flip-flops. For more information about configuration options, read the “Implementation Options” chapter in the Design Manager/Flow Engine Reference/User Guide.

    NOTE

    You cannot probe I/Os when working with an XC5200 device.

  5. Click OK to return to the Options dialog box.

  6. In the Options dialog box, click OK to return to the Implement dialog box.

  7. In the Implement dialog box, select Run to compile the design and produce the configuration data.

Creating Files for Multiple Devices (Daisy Chains)

To configure a daisy chain of devices, you need a PROM file.

  1. Produce the configuration data (BIT files) for each device, referring to the appropriate single device section.

  2. Concatenate the device BIT files using the PROM File Formatter. For more information, refer to the PROM File Formatter Reference/User Guide. Ensure that the PROM file contains the bitstreams in the same order as the devices on the target board.

NOTE

You can use a PROM file to download a daisy chain. You cannot use it to verify or debug a daisy chain.

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