Testing the Design Using a Demonstration Board

The FPGA demonstration board includes both an XC3000 family socket and an XC4000 family socket. This tutorial only targets the XC4000 family.

Preparing the Design for Readback

Locate the Calc tutorial for the XC4003E device and edit it as explained in this section to enable readback. This step is not necessary if you intend only to download your design.

1. Include the READBACK symbol in your Calc schematic using a schematic editor.
   
   
2. Connect an IBUF and an OBUF primitive to the TRIG and DATA pins of the READBACK symbol.
   
   The “Readback Symbol Connections” figure shows a detailed view of the READBACK symbol and its connections.
   
   

   Figure 9.1 Readback Symbol Connections

3. Use the MD0 and MD1 primitives if you want to use the FPGA dedicated RT and RD pins for readback.
   
   
4. Leave the CLK and RIP pins unconnected. These pins are only useful when performing readback with a microprocessor, not with the XChecker cable.
   
   

Generating a Bitstream

The next step generates a bitstream for the Calc design from the Design Manager. To generate a bitstream, you must open the implemented Calc design from the Design Manager.

NOTE

If you do not have a project for the Calc design, use the Design Manager to create a project for that design. If a project already exists for the Calc design but the project has not been updated, run the Design New Version command to read in the changes made in the schematic and to create a new version reflecting the updated schematic. Then, implement the design as explained in the “Implementing a Design” section of the Design Manager/Flow Engine Reference/User Guide.

Set the Configuration Bitstream options as explained in this section to generate a configuration file that you can use for programming, verifying, and debugging XC4000E designs. You must enable a pull-up resistor for the DONE pin, which is used for device configuration. You must also enable readback for the device.

NOTE

To generate configuration data for XC3000A devices, refer to the “Design Preparation” chapter in this manual.

1. In the Design Manager project view, select the implementation revision.
   
   
2. Select Design Implement.
   
   
3. In the Implement dialog box, click the Options button.
   
   The design implementation Options dialog box appears.
   
   
4. Select Produce Configuration Data in the Optional Targets group box.
   
   
5. Click the Edit Template button corresponding to the configuration template.
   
   The Configuration Template dialog box is displayed as shown in the “Design Manager Configuration Template Dialog Box” figure.
   
   

   Figure 9.2 Design Manager Configuration Template Dialog Box

6. Select PullUp next to the DONE pin in the Configuration Pins box to enable a pull-up resistor for the DONE pin.
   
   
7. Select Perform CRC During Configuration to perform a CRC check of your bitstream during configuration.
   
   
8. Select Produce ASCII Configuration File to create a raw bits text (RBT) file, which is an ASCII representation of your configuration bitstream.
   
   
9. Select the Readback tab.
   
   
10. Select the CCLK readback clock.
    
    
11. Select Enable Bitstream Verification and In-Circuit Hardware Debugging. This option generates the logic allocation file.
    
    

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    NOTE

    For more information about configuration options, read the “Implementation Options” chapter in the Design Manager/Flow Engine Reference/User Guide.

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12. Click OK to return to the Options dialog box.
    
    
13. In the Options dialog box, click OK.
    
    
14. In the Implement dialog box, click Run to compile the design and produce the configuration data.
    
    
15. To obtain help, click Help in the dialog box.
    
    

Connecting the Cable

To load the configuration bitstream to the demonstration board, you need one of the three available hardware cables: an XChecker cable, a parallel cable, or a serial cable. All three cables work with any of the Xilinx demonstration boards; however, the XChecker cable is the only cable that supports verification and debugging.

Before initiating the physical downloading of the design into the FPGA on a Xilinx demonstration board, you must hook up the board correctly to your computer.

You must also connect several control and power pins between the board and the cable. The bundles of leads supplied with the cables are labeled to help you connect the board to the cable.

Finally, you must connect a pair of power and ground pins to a regulated 5 volt power supply to provide power to the board and cable.

1. Plug one end of the cable into the back of your computer.
   
   If you are using a parallel cable, attach the cable to a parallel port. If you are using a serial cable or the XChecker cable, connect the cable to a serial port.
   
   
2. Connect the other end of the cable to your demonstration board. Connections from the cable to the demonstration board for downloading are shown in the “Cable Connections (Downloading)” table.
   
   
   
   

   Table 9_1 Cable Connections (Downloading)

   Cable Label	FPGA Board (XC4000E)
   VCC	J2-1
   GND	J2-3
   No Connection	J2-5
   CCLK	J2-7
   D/P	J2-9
   DIN	J2-11
   XChecker and Serial Download Cable
   PROG	J2-13
   XChecker Cable Only
   INIT	J2-15
   RST	J2-17

   
   
   
   For the FPGA demonstration board, use the leftmost column of pins, labeled J1, which is missing the pin in the third position.
   
   The “FPGA Design Demonstration Board” chapter of the Hardware User Guide discusses in detail the demonstration board and how to hook it up.
   
   
3. Connect the RT and RD pins, which are used for verification. Refer to the “Cable Connections (Verification and Debugging)” table for pin location information.
   
   
   
   

   Table 9_2 Cable Connections (Verification and Debugging)

   XChecker Cable Label	FPGA Board (XC4000E)
   CCLK	J2-7
   RT	J2-19
   RD	J2-21
   TRIG	J2-23
   CLKI	J2-25
   CLKO	J2-27

   
   
   
   
4. To perform an asynchronous debugging, which is the purpose of this tutorial, connect the RT, RD, and TRIG pins but leave the CLKI and CLKO pins unconnected.
   
   

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   NOTE

   For synchronous debugging, you would connect the RT, RD, and CLKO pins, and optionally, the TRIG and CLKI pins. See the “Connecting Your Cable” chapter for details.

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5. Ensure that the power supply is connected to the demonstration board and is turned on.
   
   The power connections for the demonstration board are shown in the “Demonstration Board Power Connections” table.
   
   

Table 9_3 Demonstration Board Power Connections

FPGA (XC4000E) Demonstration Board

Make sure the FPGA demonstration board is set up for slave mode configuration. The configuration mode for the XC4000E family part is controlled by the SW2 bank of switches. Set the switches as shown in the “SW2 Switch Settings for XC4000E Configuration” table.

Table 9_4 SW2 Switch Settings for XC4000E Configuration