Design Flow Summary

The Design Manager/Flow Engine takes EDIF netlist, XNF or PLD files from your design tool and fits them onto Xilinx devices. You can select a specific device or let the Design Manager select a device for you, based on the most economical solution that will satisfy the functional and timing parameters of the design.

Generated Reports

By default the fitter produces the following significant output files:

• Fitting report (design_name.rpt) - lists summary and detailed information about the logic and I/O pin resources used by the design, including the pinout, error and warning messages, and Boolean equations representing the implemented logic.
  
  
• Static timing report (design_name.tim) - shows a summary report of worst-case timing for all paths in the design; optionally includes a complete listing of all delays on each individual path in the design.
  
  
• Guide file (design_name.gyd) - contains all resulting pinout information required to reproduce the current pinout if the “pinfreeze” option is specified during the next invocation of the cpld command for the same design name. (The Guide file is written only upon successful completion of the fitter.)
  
  
• Programming file (design_name.jed for XC9000) - is a JEDEC-formatted (9k) programming file to be down-loaded into the cpld device.
  
  
• Timing simulation database (design_name.nga) - a binary database representing the implemented logic of the design, including all delays, consisting of Xilinx simulation model primitives (simprims).
  
  

The Design Manager contains a Report Browser for examining selected reports. If you have already run the fitter the Report Browser will contain the Fitting Report and the Translation Report, and, if you have selected timing simulation options, it will contain simulation reports. To access the Report Browser from the Design Manager:

Utilities Report Browser

The Report Browser will appear. To read any of the reports simply double-click on the appropriate report icon.

Timing Simulation

The Design Manager will optionally produce timing simulation data when you implement your design, and produce either an EDIF, VHDL or Verilog HDL formatted netlist for your simulator..