This section runs through the entire schematic design process, from creating a design to programming and simulating the design. The following device-independent design, a 4-bit Johnson counter, is used as an example:
Figure 1.2 Example 4-Bit Johnson Counter Design |  |
Simulation results for this design are shown in the “Example Viewlogic Functional Simulation Results” figure.
The design entry and simulation steps are summarized for Viewlogic and Mentor software. Other supported schematic design software will have similar procedures; refer to the appropriate Xilinx interface user guide, if applicable, or the manufacturer's documentation.
Figure 1.3 Example Viewlogic Functional Simulation Results | |
Many design entry tools have a project management facility that you can use to create a working directory for your design and to select the vendor component libraries to use in your design.
Call up the Viewlogic Project Manager by selecting the Project Manager icon in the Workview Office icon group. Create a new project named jcount.
File 
New
Select a directory and name the new project jcount.
Next, call up the libraries you need to create your design.
Project Libraries...
The Library Search Order dialog box will appear. Use this tool to add the XC9000 library, plus the builtin and simprims libraries. Use the Browse key to select directories and the Add key to add libraries. For example, browse to installation_path/viewlog/data/xc9000 (for XC9500 target devices) where installation_path is the root directory where the Xilinx software package was installed. Then click on Add and the xc9000 libraries will be added to the list. When you have all the libraries you need for the project, click on OK.
To create a working directory for your design in Viewlogic's Powerview, you would use the Project Create command.
Next, you will need to configure the design entry tool to access the Xilinx CPLD component library for schematics you develop in the project you just created. In Powerview, you would use the Project Search Order command to open a dialog window listing the configured libraries. On the first available library line, enter the directory path where the CPLD Viewlogic library is installed on your system. For example, enter installation_path/viewlog/data/xc9000 (for XC9500 target devices), where installation_path is the root directory where the Xilinx software package was installed. Under the "Library" column, enter XC9000, which is also known as the library alias. Under the Type column, select Megafile (compressed read-only format).
If you are not using the Viewlogic project manager, you can make a copy of the viewdraw.ini file in your project directory (copied from the Viewlogic standard directory) and add one of the following lines to the end of the file:
DIR [m] installation_path/viewlog/data/xc9000 (xc9000)
where installation_path is the root directory where the Xilinx software package was installed.
If you plan to simulate using Viewsim, you also need to include the Xilinx “simprims” and Viewlogic "builtin" library in the Search Order window or the viewdraw.ini file.
DIR [m] installation_path/viewlog/data/simprims (simprims)
DIR [m] installation_path/viewlog/data/builtin (builtin)
Call up the Mentor Design Manager as follows:
pld_dmgr
Select the Tools icon, the go to Tools program group and select pld_da (Design Architect).
Invoke the schematic drawing tool and draw the design. If you are using Workview Office or Powerview, you would invoke the ViewDraw tool. If you are using Mentor Graphics you would invoke pld_da (Design Architect).
If you prefer to use the completed schematic shown in “Example 4-bit Johnson Counter” figure as a sample design, you can copy the jcount schematic file from the examples directory of the Xilinx software. For Viewlogic, copy all files and subdirectories under the installation_path\viewlog\tutorial\jcount directory into your local directory (the schematic file is jcount.1 under the sch subdirectory). For Mentor select the Find Comp icon in the Design Architect and browse to installation_path\mentor\tutorial\jcount, then select jcount.
When drawing a schematic representing a CPLD device, or any sub-sheet in a CPLD design, you should not use any symbols from any other library than the Xilinx XC9000 library. For example, be careful not to use symbols from the Viewlogic builtin library. You may, however, create your own custom symbols representing sub-sheets (hierarchical schematics) or behavioral modules, as described in Chapter 2.
It is important that you label the nets that represent device input/output pins in your design. These are the nets connecting between IPAD and IBUF symbols, and between OBUF and OPAD symbols. These names will appear in the fitter reports as your pin names and will be used as your top-level signal names during timing simulation, after design implementation.
Save your schematic when finished. The Viewdraw Write command performs schematic rule checking and writes a "wire-list" file in the wir directory (wir/jcount.1).
Xilinx schematic capture libraries contain simulation models allowing you to perform functional simulation directly from your schematic. In most libraries, models for all registered symbols contain a global signal named PRLD which, when pulsed high, initializes all the flip-flops inside the symbol's model. Remember to pulse the PRLD signal high and drive all your top-level input signals (pins) to valid logic levels before running your simulation vectors.
If you are using Viewlogic, Xilinx provides a Viewsim command file for the jcount design that can be found in installation_path/viewlog/tutorial/jcount/jcount.cmd. The JCOUNT design is simulated using the following Viewsim commands:
vector Q Q[3:0]
wave jcount.wfm CLK CE CLR Q
clock c 1 0
step 50ns
h prld
h CE
l CLR
cycle
l prld
cycle 5
l CE
cycle 2
h CE
cycle 5
h CLR
cycle 2
l CLR
cycle 3
The wave command automatically invokes a ViewTrace window which displays the input and output simulation waveforms graphically.
You can functionally simulate XNF or EDIF based designs by using pld_xnf2sim or pld_edif2sim to convert the designs to a Mentor simulation model. The EDIF design must be Xilinx compatible and expressed in Unified Library components.
Performing functional simulation on a pure schematic design consists of creating a viewpoint in pld_dve from the schematic that you created in Design Architect and using pld_quicksim to simulate the design. For more information see the Mentor Graphics Interface/Tutorial Guide.
Before implementing the design, your schematic must first be translated into an EDIF 2.0.0 formatted netlist.When netlisting, make sure the netlist hierarchy stops at the Xilinx library primitives and does not expand into any functional simulation models that may exist beneath the Xilinx primitive symbols.
From Viewlogic Workview Office, go to the ViewDraw tool and select:
Tools Export EDIF
The EDIF Interfaces Dialog Box appears. Select the EDIF Netlist Writer tab and Browse to the jcount.1 schematic. Enter xilinx in the level field. To create the .edn file click once on Apply.
For Viewlogic Powerview, invoke the edifneto command and specify “XILINX” as the “level” attribute (“-l xilinx” option on the edifneto command line).
From Mentor you must convert to EDIF with the pld_men2edif utility before implementing the design with the Design Manager.
To convert your design to EDIF, follow these steps.
Start the Xilinx Design Manager. From the Windows Program Manager click on the Design Manager icon. If you are using the UNIX command line enter the following command.
dsgnmgr
From the Design Manager, create a new project and select jcount.edn as its input.
File New Project
The New Project dialog box appears. Select Browse for Input Design and find jcount.edn, then click on OK. The project should appear in the Design Manager.
Next, implement the design.
Design Implement
The Implement dialog box appears. This box allows you to select a specific Xilinx device to implement your design. Click once on Select and select for XC9500 or XC9500XL Family; leave Device, Package and Speed Grade set to AUTO. Click on OK when you have finished. Click on Run to implement the design.
Examine the reports to verify that the design was implemented as you expected. The following report files (plain text) are automatically produced by the fitter. If you are using a Design Manager you may select a report from the report browser as follows:
Utilities Report Browser
or select the report browser icon. The following reports are most useful for schematic designs:
Figure 1.4 Report Browser | |
To perform timing simulation you must extract a new EDIF netlist from the implemented design. To avoid overwriting, you may want to specify and output filename different than your design entry netlist.
The Design Manager will optionally produce timing simulation data when you implement your design. To produce timing data go to the options menu:
Design Implement
The Implementation menu will appear. Click once on the Options key to get the Options dialog box.
Select Produce Timing Simulation Data.
Go to the Interface template and select EDIF as the simulation netlist format. When the fitter runs it will generate the appropriate data. If you have already run the fitter, go back to the Flow Engine; a Timing block will appear in the flow. Press the forward arrow to resume the program from the Fit block.
In most cases, you can use the same command file you used during functional simulation to perform the timing simulation. You may need to make minor adjustments to the command file used to functionally simulate the design before it can be used to perform a timing simulation.
The typical procedure for performing a timing simulation is as follows.
See the Viewlogic Interface/Tutorial Guide for detailed information on each of the above steps.
During design implementation, the Xilinx Design Manager can produce an EDIF (EDN) file. For EDIF files, the process of timing simulation consists of converting the EDIF netlist to a Mentor EDDM model, creating a component and a viewpoint, and simulating the design with pld_quicksim.
You can now submit the design to pld_quicksim for timing simulation.
WARNINGIn order for cross-probing to work, other sessions of Design Viewpoint Editor and QuickSim must be closed. Otherwise, the interprocess communication gets confused. This includes another user's session invoked by rlogin from another workstation.
These signals will automatically be added to the QuickSim trace window. If you have a file that sets up your trace window and stimulus, use that instead. Any signals selected in the trace window will select the same on the schematic on which they reside in the DVE window. If such sheets have not been opened in DVE yet, you must open them to see the selections.
The fitter automatically creates a JEDEC programming file, jcount.jed, whenever a design is successfully implemented. Once you are satisfied with the results of the fitter (reports and timing simulation), you can download the programming file to the device using the techniques described in the JTAG Programmer Guide.
