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Retargeting a Design From a Different Family

When retargeting an existing schematic designed from a different Xilinx device family, there are three aspects of design compatibility which must be considered:

Schematic Conversion Procedure

When you re-target a design from a different Xilinx device family, you may need to perform a conversion procedure to replace the symbols in your existing schematic with symbols from the CPLD library, depending on your design entry tool. Because of the Xilinx Unified Library, such conversions are automatic and produce functionally equivalent results with little or no manual changes required. The conversion is typically performed so that the macro symbols in your design schematic link to the underlying macro schematics in the CPLD family's library rather than any other device library. Also, some primitive symbols being translated from another device library may be implemented as macro symbols in the new library, and vise-versa.

Before you convert your schematics to use a CPLD library, you should remove any symbols that do not exist in the new library, typically replacing them with similar symbols from the new library. After you convert your schematic, any unsupported symbols may no longer be visible in your schematic, and this may make it more difficult to determine the appropriate replacement logic.

NOTE

If you are converting an FPGA design containing RAM, ROM, or other elements that do not have CPLD equivalents, you cannot retarget your design unless you redesign those portions.

Using Workview Office

In this example, we are converting a schematic originally implemented using the XC3000 library into a schematic targeting the XC9000 library.

  1. Make sure the Project Manager contains the XC9000 libraries. If they do not use Project Libraries to add them. For example, browse to installation_path/viewlog/data/xc9000 where installation_path is the root directory where the Xilinx software package was installed. Then click on Add and the XC9000 libraries will be added to the list.

  2. Close all Workview Office tools except the Toolbar.

  3. Open an MS-DOS session and change the current directory to the project directory.

  4. Run the ALTRAN command with the following syntax:

    altran -l library old_alias=new_alias

    For example, to change a project from the XC3000 family to the XC9500:

    altran -l primary xc3000=xc9000

    Altran will change the library aliases in all of the schematic sheets within the specified library directory. Altran will also modify the alias of the targeted library within the Viewdraw.ini file.

  5. After running ALTRAN, open the Workview Office Project Manager. Note that the last library has the XC9000 alias but still has the path to the XC3000 library. Select ProjectLibraries to modify the Library Search Order.

  6. Select the modified library. In the Path field, change the path so it points to the XC9000 library directory. Click on Change.

  7. Select this library again. Click on the Move Up button until it is below the primary library and any user-created libraries. Click on OK.

  8. Save the changes in the Project Manager.

NOTE

When writing the EDIF file from ViewDraw for subsequent implementation in an existing Xilinx project, you must keep the same design.edn filename and project directory.

In the Design Manager window, select Design New Version. This brings up the New Version dialog box, shown in the "New Version Dialog Box" figure. The version name increments by default.

Change the name of this version, if desired, and add any comments for this version. Click OK to create this new version.

Using Viewlogic Powerview on Workstations

In this example, we are converting a Viewlogic schematic originally implemented using the XC3000 library into a schematic targeting the XC9000 library.

  1. Copy your existing schematic file(s) from the project directory used for the other device family (XC3000) into the project directory you want to use for the new target library (XC9000). For example:

    cp proj7000/sch/design1.1 proj9000/sch

  2. Use the Viewlogic project management facility (or edit the viewdraw.ini file) in your XC9000 project directory to list both the new library (XC9000) and the other family's library (XC3000) in the Search Order. For example, if you are converting an XC3000 design to XC9000, your viewdraw.ini file would contain the following two lines:

    DIR [r] installation_path/viewlog/data/xc9000 (xc9000)

    DIR [r] installation_path/viewlog/data/xc3000 (xc3000)

  3. Go to a system command window that is properly configured to run Viewlogic software. (The $path should include Viewlogic software and the $WDIR variable should be properly set.) Your current working directory should be your project directory containing the designs to be converted.

  4. Invoke the Viewlogic altran utility to automatically replace all symbols in your design from the old library (XC3000) with corresponding symbols from the new library (XC9000), as follows:

    altran -p design_name old_library=new_library

    where old_library is the library alias of the device family from which you are converting and new_library is the alias of your new target library. For example:

    altran -p design1 xc3000=xc9000

Processing a Design After Conversion

After converting a schematic from a different device family, perform the following steps, as applicable:

  1. Remove all attributes except INIT, FAST, SLOW, KEEP, BUFG, FILE, NOREDUCE and timing specifications. Change the values of PART, LOC, and PROHIBIT attributes as needed, or remove them.

  2. In the Design Manager, create a new Xilinx project for the converted schematic design.

    From the Design Manager click on the File menu and select New Project.

    Enter a new project name to use for XC9000 implementation.

    From the Target Family select XC9500.

    Before processing the design, open the Implementation Options menus and select the options available for the new device family.

  3. When you perform either functional or timing simulation, remember to pulse the PRLD signal High then Low. FPGA families may use a GSR or GR signal for initialization.

  4. If you wish to perform timing simulation, you may have to change the internal nodes you drive and monitor. The CPLD fitter optimizes the logic differently than FPGAs, which makes many of the internal nodes in the design inaccessible. However, all external signals are always visible.

Attribute Compatibility

The only schematic attributes common to FPGA devices and CPLD devices are:

The PART, LOC and PROHIBIT attributes are also used in a similar way by other families, but you must change their values when you change devices.

Any attributes contained in the converted design which are not supported by the target CPLD family should be removed from the schematic before netlisting.

Converting Behavioral Modules

If your design contains behavioral modules, you may need to perform some of these additional steps before running the fitter:

  1. If your behavioral module contains state machine logic, you may need to change the encoding style of the state machines. You generally do not have to rewrite the logic, just the state assignment. For FPGAs, which are rich in registers, one-hot encoding using symbolic state representation is most efficient. For CPLDs, which are rich in product terms, binary encoding (or other encoding that minimizes state bits) is usually most efficient. Conversion from one-hot encoding may be unnecessary for very simple state machines.

  2. If you are using a synthesis tool, recompile the behavioral module specifying XC9000 as the target technology library.

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