When you first run the fitter before your pinout is committed, the software automatically selects pin locations for your I/O signals. Pin locations are selected which will give you the greatest flexibility to iterate your design without having to move any of the pins. Each time the fitter successfully implements your design, it creates a guide file (design_name.gyd), which contains all the resulting pinout information. After you commit your pinout, subsequent design iterations cause the fitter to use the committed pinout saved in the guide file.
We strongly recommend that you allow the software to automatically generate your initial pinout. Attempting to select your own initial pin preferences reduces the ability of the fitter to implement your design successfully the first time. It further reduces the amount of logic changes you could make after freezing your pinout.
If you have successfully fit a design into a CPLD device and you build a prototype containing the device, you will probably want to "lock" the pinout.
Lock Pins. The pinout saved in the selected revision (stored in design_name.gyd) is translated into pin location (LOC) constraints and written into a user constraint file (design_name.ucf). Implement). The previous pinout information will be read from the UCF file and used in the new design revision.The pin locations stored in the guide file are specified based on the pad net names in the schematic. The pad nets are the nets that connect the IPADs to IBUFs and the OBUFs (or OBUFE or OBUFT) to OPADs (or IOPADs). If you change the label on any of the pad nets in your schematic, the pin will no longer be constrained to the location stored in the guide file.
When you iterate your design while your pins are frozen, you are free to delete existing pins and/or add new pins to your schematic. The fitter will automatically select the best locations for any new pins you add, after placing all the existing pins constrained by the guide file.
If you iterate your design and your pinout is not yet committed (you haven't built a prototype containing the device), you should not lock your pinout yet. Instead, allow the software to redefine the pinout of your modified design. This will continue to give you the greatest flexibility to alter the logic in your design again after you commit your pinout.
There are two ways to assign pins. You can use the location box in the Ports Tab window of the Constraints Editor, or you can use the LOC attribute.
The Ports Tab window of the Constraints Editor contains a Location dialog box which will create a constraint which locks a user-defined port to a specific device pin.
See the Constraints Editor User Guide for more information.
You can also assign explicit locations for pins in your design using the LOC attribute in your schematic. To assign a pin location, apply the following attribute to a pad symbol (IPAD, OPAD or IOPAD) or pad net in your schematic:
LOC=pin_name
For PC and PQ type packages, the pin_name takes the form "Pnn" where nn is a number. For example, for the PC84 package, the valid range for pin_name is P1 through P84. For grid array type packages (PG and BG), the pin_name takes the form "rc", where r is the row letter and c is the column number.
The LOC attribute cannot be applied to multi-bit pad components such as OPAD8. You must use individual pad symbols in your schematic if you want to perform pin assignment.
Whenever your design contains any LOC attributes, you should specify the target device type using the Design Manager or the schematic PART attribute (see Target Device Selection in this Chapter). LOC attributes are not always compatible when retargeting a design between different package types, device types or device families.
LOC attributes are unconditional in that the software will not attempt to relocate a pin if it cannot achieve the specified assignment. If you specify a set of LOC attributes that the fitter cannot satisfy, the fitter will terminate with an error.
If your schematic contains LOC attributes but you want to let the fitter automatically assign all I/O pins, you can set the fitter to ignore all LOC attributes. This allows you to temporarily ignore all the LOC attributes in your schematic. This is useful if you want to test how your design fits a different target device without removing all the LOC attributes from your schematic.
Go to the Flow Engine and select:
Setup Options
The Design Implementation Option menu appears. Select:
Edit Template
Then select the tab:
Basic
Lastly, remove the check in the box adjacent to Use Design Location Constraints. Then click OK.
You can explicitly assign internal nodes in your design to specific function blocks or even specific macrocells of the target device. To assign an internal node to a specific location, apply the following attribute to a symbol or its output net:
LOC=FBnn[_mm]
where nn is a valid function block number and mm (optional) is a valid macrocell number for the target device.
The PROHIBIT attribute allows you to reserve device pins for later use, or simply prevent them from being used at all. For instance, if you anticipate design changes in the future and want to set traces on your printed circuit board now, you can use PROHIBIT to prevent the fitter from using pins associated with those traces. Then, when you decide to use the traces, you can use the LOC attribute to assign those pins to new input/output buffers you place in your design. To use PROHIBIT, instantiate a CONFIG symbol and attach the PROHIBIT attribute to it. The syntax is as follows:
PROHIBIT=Pnn[,Pnn]...
where nn is the pin number for PC, PQ and VQ packages, and rc (row,column) for BG or PG packages.
In the Constraints Editor, Prohibit I/O Locations prevents all selected I/O pins from being used by the design. This dialog can be entered using a dialog box provided in the Ports tab.
You can apply the LOC and PROHIBIT attributes to as many pad symbols in your design as you like. However, each pin assignment further constrains the software making it more difficult for the fitter to automatically allocate logic and I/O resources for the remaining I/O signals in your design.
When you manually assign output and I/O pins, you force the software to place associated logic functions into specific macrocells and specific function blocks. If the associated logic does not exceed the available function block resources (macrocells, product terms, and FastCONNECT inputs), the logic is mapped into the macrocell and the design will route in the FastCONNECT.
It is usually best to allow the fitter to automatically assign most or all of the pins based on the most efficient placement of logic in the device. The fitter automatically establishes a pinout which best allows for future design iterations without pin relocation. Any manual pin assignments you make in your design may not allow as much tolerance for changes in the logic associated with those pins, and in the logic physically mapped to nearby locations in the device.
If you are assigning pin locations to signals used as clocks, asynchronous set/reset, or output enable in your design, you should assign them to the GCK, GSR and GTS pins on the device if you want to take advantage of these global resources. The fitter will still automatically assign other clock, set/reset and output enable inputs to remaining GCK, GSR and GTS pins if available.
