Controlling Logic Optimization

When you build combinational logic functions using simple gates and inverters, or when you use macros that contain gate-level logic paths, the software attempts to collapse as much of the logic as possible into the smallest number of CPLD macrocells. Any combinational logic function bounded between device I/O pins and flip-flops is subject to complete or partial collapsing. Collapsing the logic improves the speed of the logic path and can also reduce the amount of logic resources (macrocells, p-terms and FastCONNECT inputs) required to implement the function.

The process of collapsing logic into other logic functions is called "logic optimization".

Collapsing Product Term Limit

When a larger combinational logic function consisting of several levels of AND-OR logic is completely collapsed (flattened), the number of product terms required to implement the function may grow considerably. By default, the fitter limits the number of p-terms used as a result of collapsing to 20. If the collapsing of a logic level results in a logic function consisting of more than the p-term limit (after Boolean reduction), then the collapsing of that logic level is not performed and the function will be implemented using two or more levels of AND-OR logic.

Controlling Pterm Limits in Design Manager

In Design Manager, controlling the Pterm limits is performed as follows:

1. Go to the Flow Engine and select:
   
   Setup Options
   
   
2. The Design Implementation Option menu appears. Select:
   
   Edit Template
   
   
3. Then select the menu:
   
   Advanced
   
   
4. Lastly, place a value in the box adjacent to Collapsing Pterm Limit.
   
   

The allowable range for the p-terms parameter is between 5 and 90; the default is 20.

If the Path Delay is Not Satisfactory

If you find that the path delay of a larger, multi-level logic function is not satisfactory, try increasing the p-term limit parameter to allow the larger functions to be flattened further. For example, you may try increasing the p-term limit to 25, 30 or 35 when rerunning the fitter.

The fitter report (design_name.rpt) indicates the number of p-terms used for each logic function. You should see these numbers increase as you raise the pterms limit, until the design is fully flattened. At the same time, you'll see the internal combinational nodes eliminated until none remain.

Preventing Collapsing of a Logic Node

Flattening typically increases the overall amount of p-term resources required to implement the design. Some designs which fit the target device initially may fail to fit if flattened too much. Other designs can be flattened completely and still fit. If you cannot increase the pterms parameter enough to sufficiently flatten a critical path and still fit the target device, you may try applying the logic optimization control attribute KEEP to specific nodes in your design.

Applying the following attribute to a logic symbol or net in the middle of a logic function prevents collapsing of that logic node into its fan-outs:

KEEP

You can use KEEP to break logic chains in non-speed-critical paths and prevent those functions from collapsing and using too many p-terms. If you set the p-term limit parameter too high and your design no longer fits, try using KEEP to reduce the size of selected non-critical paths.

The KEEP attribute has no effect on any symbol that contains no macrocell logic, such as an I/O buffer.

When the KEEP attribute is placed on a symbol, it inhibits logic optimization on all macrocells used to implement the symbol. For example, if you place KEEP on a macro symbol (like D2_4E), all outputs and internal nodes of the decoder will be prevented from collapsing. This is usually not desirable.

If you want to prevent collapsing on a specific output signal from a macro symbol, you can place the KEEP attribute on the net itself. When you place the KEEP attribute on a net, the fitter applies the attribute only to the primitive symbol that drives that net.

Forcing Collapsing of a Logic Node

You can also force a logic symbol to collapse into all of its fanouts by placing the following attribute on the symbol or its output net:

COLLAPSE

The collapse attribute affects all logic functions contained within a symbol. If you want to force collapsing of a multi-symbol logic chain, you may need to use multiple collapse attributes.

Multilevel Logic Optimization

Multilevel Logic Optimization seeks to simplify the total number of logic expressions in a design, and then collapse the logic in order to meet user objectives such as density, speed and timespecs. This optimization targets CPLD architecture, making it possible to collapse to the macrocell limits, reduce levels of logic, and minimize the total number of pterms.

Multilevel Logic Optimization extracts combinational logic from your design. Combinational logic includes:

• register-to-register logic
  
  
• path-to-register logic
  
  
• register-to-path logic
  
  
• path-to-path logic
  
  

Multilevel Logic Optimization operates on combinational logic according to the following rules:

1. If timespecs are set, the program will optimize for speed to meet timespecs.
   
   
2. If timespecs are not set, the program will optimize either for speed or density, depending on the user setting of Timing Optimization.
   
   
   1. If Timing Optimization is turned on, the combinational logic will be mapped for speed.
      
      
   2. If Timing Optimization is turned off, the combinational logic will be mapped for density. The goal of optimization will then be to reduce th total number ot pterms.
      
      
3. Logic marked with the attribute NOREDUCE will not be extracted or optimized.
   
   

Setting Multilevel Logic Optimization

Multilevel Logic Optimization can be set from the Advanced tab of the Implementation Options template of the Design Manager as follows:

1. Design Implement
   
   
2. Press the Options softkey.
   
   
3. Select Edit Template
   
   
4. Select the Advanced tab.
   
   
5. Place a check in the Use Multilevel Logic Optimization box (the default is On).
   
   

Multilevel Logic Optimization will operate when you run the fitter.