XC9500 devices can emulate tristate bussing using special gates that disable the macrocell feedback path to the FastCONNECT matrix. XC9500XL devices do not support internal tristate buffers. Do not use BUFE or BUFT components in XC9500XL designs.
Three methods of multiplexing tristate signals are shown in the “Methods of Multiplexing Tristate Signals” figure. Which method you choose depends on your application, resources, and speed requirements, although method C, which uses a multiplexer, is usually best for CPLD designs.
Method A, shown in the “Methods of Multiplexing Tristate Signals” figure, part A, uses tristate buffers instead of a multiplexer. The advantage of method A over method C is that method A uses only one Function Block input in the macrocell that sends the signal off-chip. The disadvantage of method A is that macrocell feedback is not available to any other on-chip functions because the internal feedbacks are tristated; therefore counters will not work with Method A, but will work with Method C.
Method B, shown in the “Methods of Multiplexing Tristate Signals” figure, part B, requires that you tie the signals together off-chip. This method results in a short clock-to-out delay and uses fewer macrocells than methods A and C. However, it uses more pins than method A or C.
Method C, shown in the “Methods of Multiplexing Tristate Signals” figure, part C, uses a multiplexer instead of tristate buffers. This method results in a longer clock-to-out delay than method B. To shorten the clock-to-output delay would require pipelining the output of the multiplexer using a flip-flop and asserting the select signals one clock cycle in advance. This method uses more macrocells than method B, but uses fewer pins.
Figure 4.3 Methods of Multiplexing Tristate Signals |  |
