The simple expression of a D-type latch contains inherent logic hazards which could result in unpredictable results when run through the fitter.
Figure 4.4 Simple Mux and Cross-Coupled-NAND Latches |  |
A timing malfunction can occur if the logic is divided between two separate macrocells by the fitter. The “Malfunction of Physical Implementation” figure illustrates what can happen.
Figure 4.5 Malfunction of Physical Implementation | |
If you implement the D-type latches with proper redundant logic, the problem will not occur. The “D-type Latch Solutions” figure shows two solutions for schematic implementation of D-type latches.
Figure 4.6 D-type Latch Solutions | |
When you create redundant logic in a schematic, remember to specify the NOREDUCE attribute on the final output gate to prevent the software's Boolean minimization routine from removing the redundant logic
