Appendix A

UCF Syntax

This appendix describes the UCF syntax for constraints created with the Constraints Editor. It contains the following sections.

• “Group Elements Associated by Nets (TNM_Net)”
  
  
• “Group Elements by Instance Name (TNM)”
  
  
• “Group Elements by Element Output Net Name Schematic Users (TIMEGRP)”
  
  
• “Timing THRU Points (TPTHRU)”
  
  
• “Pad to Setup”
  
  
• “Clock to Pad”
  
  
• “Slow/Fast Path Exceptions (FROM TO)”
  
  
• “Multicycle Paths (FROM TO)”
  
  
• “False Paths (FROM TO TIG)”
  
  
• “False Paths by Net (Net TIG)”
  
  
• “Period”
  
  
• “Location”
  
  
• “Prohibit I/O Locations”
  
  
• “FAST/SLOW”
  
  
• “PULLUP/PULLDOWN”
  
  
• “DRIVE”
  
  
• “IOSTANDARD (Virtex devices only)”
  
  

• “VOLTAGE”
  
  
• “TEMPERATURE”
  
  

Group Elements Associated by Nets (TNM_Net)

Identifies the nets that make up a group which can then be used in a timing specification. A TNM_NET (timing name for nets) is an attribute that can be used to identify the elements that make up a group which can then be used in a timing specification. Essentially TNM_NET is equivalent to TNM on a net except for pad nets.

NET netname TNM_Net=identifier;

netname is the name of a net. identifier is a value that consists of any combination of letters, numbers, or underscores.

Group Elements by Instance Name (TNM)

Identifies the instances that make up a group which can then be used in a timing specification. A TNM (pronounced tee-name) is a flag that you place directly on your schematic to tag a specific net, element pin, primitive or macro. All symbols tagged with the TNM identifier are considered a group.

INST instance_name TNM=identifier;

instance_name can be FFs, All Pads, Input Pads, Output Pads, Bi-directional Pads, Tri-stated Output Pads, RAMs, or Latches.

identifier is a value that consists of any combination of letters, numbers, or underscores. Keep it short for convenience and clarity.

Group Elements by Element Output Net Name Schematic Users (TIMEGRP)

Specifies a new group with instances of FFs, PADs, RAMs, LATCHES, or User Groups by output net name.

UCF Syntax

TIMEGRP identifier= element (output_netname);

identifier is the name for the new time group.

element can be FFs, All Pads, Input Pads, Output Pads, Bi-directional Pads, Tri-stated Output Pads, RAMs, or Latches, or User Groups.

output_netname is the name of the net attached to the element.

Timing THRU Points (TPTHRU)

Identifies an intermediate point on a path.

INST instance_name TPTHRU=identifier;

NET netname TPTHRU=identifier;:

identifier is a unique name.

Pad to Setup

Specifies the timing relationship between an external clock and data at the pins of a device. Operates on pads or predefined groups of pads.

OFFSET=IN time unit BEFORE pad_clock_netname;

[NET pad_netname] OFFSET IN time unit BEFORE pad_clock_netname;

[TIMEGRP padgroup_name] OFFSET=IN time unit BEFORE pad_clock_netname[TIMEGRP reg_group_name];

padgroup_name is the name of a group of pads predefined by the user.

reg_group_name is the name of a group of registers predefined by the user.

pad_clock_netname is the name of the clock at the port.

For more information on Pad to Setup, see the “From the Global Tab Window” section in the "Using the Constraints Editor" chapter.

Clock to Pad

Specifies the timing relationship between an external clock and data at the pins of a device. Operates on pads or predefined groups of pads.

OFFSET=OUT time unit AFTER pad_clock_netname;

NET pad_netname OFFSET=OUT time unit AFTER pad_clock_netname ;

TIMEGRP padgroup_name OFFSET=OUT time unit AFTER pad_clock_netname [TIMEGRP reg_group_name];

padgroup_name is the name of a group of pads predefined by the user.

reg_group_name is the name of a group of registers predefined by the user.

pad_clock_netname is the name of the clock at the port.

For more information on Clock to Pad, see the “From the Global Tab Window” section in the "Using the Constraints Editor" chapter.

Slow/Fast Path Exceptions (FROM TO)

Establishes an explicit maximum acceptable time delay between groups of elements.

TIMESPEC TSid=FROM source_group TO destination_group time [unit];

TIMESPEC TSid=FROM source_group THRU timing_point TO destination_group time [unit];

source_group and destination_group are FFS, RAMS, PADS, LATCHES, or user-created groups.

timing point is an intermediate point as specified by the TPTHRU constraint on the Advanced tab window.

Multicycle Paths (FROM/THRU/TO)

Establishes a maximum acceptable time delay between groups of elements relative to another timing specification.

TIMESPEC TSid=FROM source_group TO destination_group time [unit];

TIMESPEC TSid=FROM source_group THRU timing_point TO destination_group time [unit];

source_group and destination_group are FFS, RAMS, PADS, LATCHES, or user-created groups.

timing point is an intermediate point as specified by the TPTHRU constraint on the Advanced tab window.

False Paths (FROM TO TIG)

Marks paths between a source group and a destination group that are to be ignored for timing purposes.

TIMESPEC TSid=FROM source_group TO destination_group TIG;

TIMESPEC TSid=FROM source_group THRU timing_point(s) TO destination_group TIG;

source_group and destination_group are FFS, RAMS, PADS, LATCHES, or user-created groups.

timing point is an intermediate point as specified by the TPTHRU Points constraint on the Advanced tab window.

False Paths by Net (Net TIG)

Marks nets that are to be ignored for timing purposes.

NET netname TIG;

NET netname TIG=TSid1 ... TSidn;

Period

Defines a clock period.

TIMESPEC TSid=PERIOD timegroup_name time | TSid [unit] [HIGH | LOW high_or_low_time unit];

id is a unique identifier. The identifier can consist of letters, numbers, or the underscore character (_).

unit is picoseconds, nanoseconds, microseconds, or milliseconds.

HIGH | LOW indicates the state of the first pulse of the clock.

Location

Locks a user-defined port to a device pin.

NET pad_netname LOC=location;

location is a device pin identification, for example, P10.

Prohibit I/O Locations

Disallows the use of an I/O site by PAR (Place and Route) and FPGA Editor.

CONFIG PROHIBIT=location1, [location2..., locationn];

location is a pin location identification.

FAST/SLOW

Assigns a slew rate to a selected port

Net port_netname FAST|SLOW;

port_netname is the name of the port.

PULLUP/PULLDOWN

Signifies a pull level (PULLUP, PULLDOWN, or KEEPER)for a selected output port. KEEPER is used for Virtex devices only. When a tri-state buffer goes to high impedance, KEEPER keeps the input level of the buffer on the pad net.

NET port_netname PULLUP| PULLDOWN |KEEPER;

port_netname is the name of the net attached to the port.

DRIVE

This constraint assigns a signal strength to a selected port.

NET port_netname DRIVE=value;

port_netname is the name of the net attached to the port.

value is drive strength (in mA). Values vary for different devices.

IOSTANDARD (Virtex devices only)

Assigns an input/output standard to a selected net attached to the port.

NET port_netname IOSTANDARD=standard_name

port_netname is the name of the net attached to the port.

standard_name is the name of the I/O standard (LVTTL, LVCMOS, and so forth). See the “Attributes, Constraints, and Carry Logic” chapter in the Libraries Guide.

VOLTAGE

Allows you to specify operating voltage. This provides a means of prorating delay characteristics based on the specified voltage.

VOLTAGE=value[units];

value is an integer or real number specifying the voltage and units is an optional parameter specifying the unit of measure.

TEMPERATURE

Allows the specification of the operating temperature which provides a means of prorating device delay characteristics based on the specified junction temperature. Prorating is a linear scaling operation on existing speed file delays and is applied globally to all delays.

TEMPERATURE=value;

value is an integer or real number specifying the temperature in Celsius.