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This appendix contains definitions and explanations for terms used in this manual.
Asynchronous debugging is a debugging mode in which you capture data without controlling your system clock.
BIT file is the same as a bitstream file. See bitstream.
A bitstream file is a stream of data that contains location information for logic on a device, that is, the placement of Configurable Logic Blocks (CLBs), Input/Output Blocks (IOBs), TBUFs, pins, and routing elements. The bitstream also includes empty placeholders that are filled with the logical states sent by the device during a readback. Only the memory elements, such as flip-flops, RAMs, and CLB outputs, are mapped to these placeholders, because their contents are likely to change from one state to another. When downloaded to a device, a bitstream configures the logic of a device and programs the device so that the states of that device can be read back.
A bitstream file has a .bit extension.
A block is a group of one or more logic functions.
Bottom-up design is an HDL design methodology where already defined HDL blocks are merged into one overall desired design behavior. The lowest level portion of your design is completed first. Only after the low-level building blocks are complete do you finish higher-level hierarchical blocks in your design. This methodology is typically used with schematic capture programs.
A BUFT is a tristate buffer.
A byte-wide PROM is a byte-wide programmable read-only memory (PROM) supplies data one byte at a time.
The CCLK pin is the XChecker pin that provides the configuration clock for the device or daisy chain of devices during a download.
The CLKI pin is the clock input pin to XChecker. CLKI provides an external clock to the Hardware Debugger so that in conjunction with the CLKO pin, the Debugger can control the application of the external clock to the device being debugged.
The CLKO pin is the XChecker clock output pin. CLKO supplies the Hardware Debugger controlled clock to the device being debugged. The source of CLKO is one of the following: CLKI, logic 1, logic 0, or the internal XChecker clock.
A clock input path starts at either an input of the chip or at the output of a flip-flop, latch, or RAM, and ends at any clock pin on a flip-flip or latch enable. The clock input path time is the maximum time required for the signal to arrive at the flip-flop clock input. Clock input paths help to determine system-level design timing.
Clock skew is the difference between the time a clock signal arrives at the source flip-flop in a path and the time it arrives at the destination flip-flop. It is also referred to as clock delay.
A critical path is a signal in a section of combinatorial logic that limits the speed of the logic. Storage elements begin and end a critical path, which may include I/O pads.
A daisy chain is a series of bitstream files concatenated in one file. It can be used to program several FPGAs connected in a daisy chain board configuration.
Debugging is the process of reading back or probing the states of a configured device to ensure that the device is behaving as expected while in circuit.
In an FPGA, the DIN pin loads a bitstream in serial mode. On the XChecker cable, it provides the bitstream data and connects to the DIN pin of the target FPGA.
The DONE pin is a dual function pin. As an input, it can be configured to delay the global logic initialization or the enabling of outputs. As an output, it indicates the completion of the configuration process.
Note: For Virtex devices, this pin is called DONE_CFG.
Downloading is the process of configuring or programming a device by sending bitstream data to the device.
The D/P pin is dual-function pin. As an input, it initiates a reconfiguration of a configured device. As an output, it signals the end of configuration.
EDIF is an acronym for Electronic Data Interchange Format, an industry standard file format for specifying a design netlist. It is generated by a third-party design-entry tool.
This is a PROM format supported by the Xilinx tools. Its maximum address is 16 777 216. This format supports PROM files of up to (8 x 16 777 216) = 134 217 728 bits.
The external clock is the system clock that XChecker uses from the target board during synchronous mode debugging. To use an external clock, connect the system clock to the XChecker cable using the CLKI pin and the XChecker clock to the FPGA device using the CLKO pin.
Fitting is the process of putting logic from your design into physical macrocell locations in the CPLD. Routing is performed automatically, and because of the UIM architecture, all designs are routable.
A GND pin is Ground (0 volts).
A group is a collection of common signals to form a bus. In the case of a counter, for example, the different signals that produce the actual counter values can be combined to form an alias, or group.
A guide file is a previously placed and routed FPGA or fitted CPLD file that can be used in a subsequent place and route or fitting operation.
HDL is an acronym for Hardware Description Language. The most common HDLs in use today are Verilog and VHDL. They describe designs in a technology-independent manner using a high level of abstraction.
HEX refers to a simple text dump of the PROM data in HEX format. It has unlimited data capacity.
Hold time is the time following a clock event during which the data input to a latch or flip-flop must remain stable in order to guarantee that the latched data is correct.
The INIT pin is a device pin indicating when a device is ready to receive configuration data after power-up.
An instance is one specific gate or hierarchical element in a design or netlist. The term “symbol” often describes instances in a schematic drawing. Instances are interconnected by pins and nets. Pins are ports through which connections are made from an instance to a net. A design that is flattened to the lowest level constituents is described using primitive instances.
The internal XChecker clock is internal to XChecker and can be applied by the XChecker CLKO pin to a device being debugged.
An IOB is a collection or grouping of basic elements that implement the input and output functions of an FPGA device.
The .ll file is the logic allocation file, which indicates the bitstream position of storage elements such as latches, flip-flops, and IOB inputs and outputs. The Hardware Debugger uses this file to locate signal values inside a readback bitstream.
Loading direction is the direction of the addresses in which data is stored on your PROM. In the Up direction, the data is stored in ascending order. In the Down direction, the data is stored in descending order.
A logic icon is a graphical representation of a logic resource, such as a flip-flop, buffer, or register.
Logic synthesis is a process that starts from a high level of logic abstraction (typically Verilog or VHDL) and automatically creates a lower level of logic abstraction using a library containing primitives.
Mapping is the process of assigning a design's logic elements to the specific physical elements that actually implement logic functions in a device.
MCS-86 is a PROM format supported by the Xilinx tools. Its maximum address is 1 048 576. This format supports PROM files of up to (8 x 1 048 576) = 8 388 608 bits.
A net is a logical connection between two or more symbol instance pins. After routing, the abstract concept of a net is transformed to a physical connection called a wire.
The number of clock cycles is the number of clocks that occur between snapshots during synchronous mode debugging. When capturing multiple snapshots, the number of snapshots is used as a trigger for capturing each snapshot.
In the context of Xilinx FPGA devices, one-to-one logic is the exact correspondence between the logic specified in the design entry phase and the logic implemented in the device. For example, if you draw three inverters in your design, there are three corresponding inverters in the programmed device. This correspondence makes back-annotation of timing delays very straightforward and ensures that there are no differences between your original design and the finished device.
Optimization is the process that decreases the area or increases the speed of a design.
A pad is the physical bonding pad on an integrated circuit. All signals on a chip must enter and leave by way of a pad. Pads are connected to package pins in order for signals to enter or leave an integrated circuit package.
A pin can be a symbol pin or package pin. A package pin is a physical connector on an integrated circuit package that carries signals into and out of an integrated circuit. A symbol pin, also referred to as an instance pin, is the connection point of an instance to a net.
Place effort is a user-controlled parameter that balances run-time with placement efficiency for the Flow Engine.
The placer is a utility that maps logic from your design into specific locations in the target FPGA chip.
Placing is the process of assigning physical device cell locations to the logic in a design.
A primitive is a logic element that directly corresponds, or maps, to a basic silicon component.
Probing is the process of examining the states of an FPGA device.
A !PROG pin is an XChecker pin that provides a reprogram pulse to XC4000, XC5200, and Virtex devices when connected to the !PROG pin of the device.
Programming is the process of configuring the programmable interconnect in the FPGA.
PROM is an acronym for programmable read-only memory.
A PROM file consists of one or more BIT files (bitstreams) formed into one or more datastreams. The file is formatted in one of four industry-standard formats: Intel MCS-86, Tektronics TEKHEX, Motorola EXORmacs, or HEX. The PROM file includes headers that specify the length of the bitstreams, as well as all the framing and control information necessary to configure the FPGAs. It can be used to program one or more devices.
An RBT file is a raw BIT format file; the ASCII version of the BIT file.
The RD pin is the XChecker readback data pin.
Readback is the process of reading the logic downloaded to an FPGA device. There are two types of readbacks.
Route effort is the user-controlled parameter that balances run-time with routing efficiency for the Flow Engine.
The router connects all appropriate pins to create the design's nets.
Routing is the process of assigning logical nets to physical wire segments in the FPGA that interconnect logic cells.
A Relationally Placed Macro (RPM) defines the spatial relationship of the primitives that constitute its logic. An indivisible block of logic elements that are placed as a unit into a design.
An RST pin is an XChecker pin that can be driven Low after configuration to reset the target FPGA internal latches and flip-flops.
The RT pin is the XChecker readback trigger pin.
A schematic is a hierarchical drawing representing a design in terms of user and library components.
A script is a series of commands that automatically execute a complex operation such as the steps in a design flow.
Standard Delay Format (SDF) is an industry-standard file format for specifying timing information. It is usually used for simulation.
A serial PROM is a PROM that is read one bit at a time.
Setup time is the time prior to a clock event during which the data input to a latch or flip-flop must remain stable in order to guarantee that the latched data is correct.
A snapshot is the readback data that contains the values of all storage elements, CLB outputs, and IOB inputs and outputs of a design at a point in time.
A state is a set of values stored in the memory elements of a device (flip-flops, latches, RAMs, CLB outputs, and IOBs) that represent the state of that device for a particular readback. To each state there corresponds a specific set of logical values.
Static timing analysis is a point-to-point delay analysis of a design network.
The status bar is an area located at the bottom of a window that provides information about the commands that you are about to select or that are being processed.
Synchronous debugging is a debugging mode in which you use the XChecker cable to have full control of the clock.
See logic synthesis.
A TCK pin is an XChecker pin. This output supplies clocks for a boundary scan port on an XC9500 device. The JTAG software must be used to drive the boundary scan port on the XChecker cable.
A TDI pin is an XChecker pin. This input receives data from the boundary scan chain. The JTAG software must be used to drive the boundary scan port on the XChecker cable.
TEKHEX is a PROM format supported by Xilinx. Its maximum address is 65 536. This format supports PROM files of up to (8 x 65 536) = 524 288 bits.
Timing is the process that calculates the delays associated with each of the routed nets in the design.
Timing constraints are user specifications of the maximum allowable delay on any given set of paths in a design. Timing constraints can be entered on a schematic or in a user constraints file (UCF).
A TMS pin is an XChecker pin. This output drives the mode of the boundary scan state machine. The JTAG software must be used to drive the boundary scan port on the XChecker cable.
The toolbar is a field located under the menu bar at the top of a window. It contains a series of buttons that you click to execute some of the most commonly used commands. These buttons are an alternative to the menu commands.
The toolbox is a field located in the Design Manager main window. It contains a series of buttons that you click to invoke tools such as the Flow Engine, Timing Analyzer, Floorplanner, Hardware Debugger, PROM File Formatter, FPGA Editor, Chip Viewer, and JTAG Programmer.
Top-down design starts a design with the highest level of abstraction and gradually designs underlying blocks until the complete design is implemented in the target technology. Top-down design is often technology-independent at the highest levels of design abstraction.
A TRIG pin is an XChecker external trigger pin that causes the Hardware Debugger to initiate a readback of the device being debugged.
A trigger is an external signal that tells the Hardware Debugger to start the readback operation. It applies the clock to the bitstream.
TTY is a textual command line interface.
The UIM is the routing matrix for CPLD devices. This fully populated switching matrix allows any output to be routed to any input, guaranteeing 100% routability of all designs. The UIM can also function as a very wide AND gate, which can allow more logic to be placed in macrocells.
The VCC pin is Power (5 volts). It is the supply voltage.
Verification is the process of reading back the configuration data of a device and comparing it to the original design to ensure that all of the design was correctly received by the device.
Verilog is a commonly used Hardware Description Language (HDL) that can be used to model a digital system at many levels of abstraction ranging from the algorithmic level to the gate level. It is IEEE standard 1364-1995. Verilog was originally developed by Cadence Design Systems and is now maintained by OVI.
A Verilog file has a .v extension.
VHDL is an acronym for VHSIC Hardware Description Language (VHSIC an acronym for Very High-Speed Integrated Circuits). It can be used to describe the concurrent and sequential behavior of a digital system at many levels of abstraction ranging from the algorithmic level to the gate level. VHDL is IEEE standard 1076-1993.
A VHDL file has a .vhd or .vhdl extension.
A waveform is a graphical representation of a set of simulation transitions that depicts the digital or electrical values of a node on the schematic.
Viewlogic netlist files built by ViewDraw, PROcapture, or ViewSynthesis.
A WIR file is an intermediate design file generated by the Viewlogic design tools.
In the PROM File Formatter, the workspace is a frame and an empty datastream. When you add files into the datastream, the horizontal arrows indicate the concatenation of files.