XC9500 Simulation Options

Click the General, VHDL/Verilog, or EDIF tab to access the different options within the Simulation Options dialog box. Use the different tabs of this dialog box to set the options described in this section.

Click OK to accept the options, click Cancel to exit the dialog box without changing any settings, click Default to set the default options, or click Help to obtain online help.

XC9500 General Tab

Use this tab, shown in the following figure, to set the following options.

Figure 5.70 XC9500 General Tab

Simulation Data Options

Specify the netlist format to use for simulation. The following formats are available.

• EDIF
  
  
• VHDL
  
  
• Verilog
  
  

Simulation Netlist Name

Select this option to specify the name of the output file. This allows you to control the output netlist name to avoid overwriting any files. The default name is time_sim.

XC9500 VHDL/Verilog Tab

Use this tab, shown in the following figure, to set the VHDL or Verilog options.

Figure 5.71 XC9500 VHDL/Verilog Tab

The XC9500 VHDL/Verilog tab is identical to the tab described in the “Spartan VHDL/Verilog Tab” section.

XC9500 EDIF Tab

Use this tab, shown in the following figure, to set the EDIF options.

Figure 5.72 XC9500 EDIF Tab

The XC9500 EDIF tab is identical to the tab described in the “Spartan EDIF Tab” section.