Design Manager/Flow Engine Guide

About This Manual

This manual describes the Xilinx Design Manager and Flow Engine, tools that manage and process your design implementation. This manual describes the use of these tools with the Xilinx Alliance Series software. Because the Design Manager and Flow Engine are closely integrated in the Alliance Series, this manual covers both software applications in detail and also covers how to access other tools from the Design Manager.

In the Xilinx Foundation Series software, the Project Manager, rather than the Design Manager, is the top level software tool that is closely integrated with the Flow Engine. For information on the Foundation Series Flow Engine, refer to this manual. For information on the Project Manager, see the Foundation Series User Guide.

Note: The Design Manager software documented in this manual is available as a standalone tool from the Foundation Series software. Use the Xilinx Foundation Series Accessories Design Manager command to access the standalone Design Manager.

Additional Resources

For additional information, go to http://support.xilinx.com. The following table lists some of the resources you can access from this page. You can also directly access some of these resources using the provided URLs.

Resource	Description/URL
Tutorial	Tutorials covering Xilinx design flows, from design entry to verification and debugging http://support.xilinx.com/support/techsup/tutorials/index.htm
Answers Database	Current listing of solution records for the Xilinx software tools Search this database using the search function at http://support.xilinx.com/support/searchtd.htm
Application Notes	Descriptions of device-specific design techniques and approaches http://support.xilinx.com/apps/appsweb.htm
Data Book	Pages from The Programmable Logic Data Book, which describe device-specific information on Xilinx device characteristics, including readback, boundary scan, configuration, length count, and debugging http://support.xilinx.com/partinfo/databook.htm
Xcell Journals	Quarterly journals for Xilinx programmable logic users http://support.xilinx.com/xcell/xcell.htm
Tech Tips	Latest news, design tips, and patch information on the Xilinx design environment http://support.xilinx.com/support/techsup/journals/index.htm

Manual Contents

This manual covers the following topics.

Chapter 1, “Introduction,” describes the Design Manager and Flow Engine main functions, place in the Xilinx design flow, key features, inputs and outputs, and the architectures with which they work. It also outlines the basic procedure for using the tools.
Chapter 2, “Getting Started,” describes how to start and exit the Design Manager and Flow Engine; how to use the menus, icons, and dialog boxes; and how to use online help.
Chapter 3, “Using the Design Manager and Flow Engine,” explains how to perform Design Manager and Flow Engine functions.
Chapter 4, “Menu Commands,” describes the Design Manager and Flow Engine menu commands and options.
Chapter 5, “Implementation Flow Options,” describes the options you can set to control the implementation flow.
Appendix A, “Glossary,” defines important words, terms, concepts, and ideas used in this manual.
Appendix B, “Legacy Information,” describes major changes to the software since the previous release.

Conventions

This manual uses the following typographical and online document conventions. An example illustrates each typographical convention.

Typographical

The following conventions are used for all documents.

Courier font indicates messages, prompts, and program files that the system displays.

speed grade: -100
Courier bold indicates literal commands that you enter in a syntactical statement. However, braces “{ }” in Courier bold are not literal and square brackets “[ ]” in Courier bold are literal only in the case of bus specifications, such as bus [7:0].

rpt_del_net=

Courier bold also indicates commands that you select from a menu.

File Open
Italic font denotes the following items.
- Variables in a syntax statement for which you must supply values
  
  edif2ngd design_name
- References to other manuals
  
  See the Development System Reference Guide for more information.
- Emphasis in text
  
  If a wire is drawn so that it overlaps the pin of a symbol, the two nets are not connected.
Square brackets “[ ]” indicate an optional entry or parameter. However, in bus specifications, such as bus [7:0], they are required.

edif2ngd [option_name] design_name
Braces “{ }” enclose a list of items from which you must choose one or more.

lowpwr ={on|off}
A vertical bar “|” separates items in a list of choices.

lowpwr ={on|off}
A vertical ellipsis indicates repetitive material that has been omitted.

IOB #1: Name = QOUT' IOB #2: Name = CLKIN' . . .
A horizontal ellipsis “. . .” indicates that an item can be repeated one or more times.

allow block block_name loc1 loc2 ... locn;

Online Document

The following conventions are used for online documents.

Red-underlined text indicates an interbook link, which is a cross-reference to another book. Click the red-underlined text to open the specified cross-reference.
Blue-underlined text indicates an intrabook link, which is a cross-reference within a book. Click the blue-underlined text to open the specified cross-reference.