Design Manager Fundamentals

You can perform multiple functions from within the Design Manager, such as launching Xilinx tools and managing your projects, design versions, and implementation revisions.

Projects

The Design Manager window displays all Xilinx data related to a single project. When you create a project, a design version and implementation revision are automatically created so you always have a revision on which to run the software tools. A project includes all design versions and implementation revisions that are created as you implement your design. You can work with multiple projects, but only one is active at a time. The hierarchical structure in the Design Manager project view shows the relationships of the data elements to each other.

Design Versions

You create your design using third party front-end tools that support schematic and Hardware Description Language (HDL) entry. The Design Manager reads in the design netlist and creates a design version in the Design Manager project view. If the design netlist changes, the Design Manager reads in the modified design and creates a new design version.

You can try modified versions of your design and easily keep track of them. Each new set of changes becomes a new design version and is assigned a design version name by the Design Manager. You can choose any one of the available design versions for processing.

When you create a new design version, a new implementation revision is automatically created. Each design version can contain multiple implementation revisions.

Note: The Design Manager saves design versions in the Xilinx database format, not in the format of the front-end editor.

Implementation Revisions

After you create a design version, you can try different implementation strategies on your design. The data associated with each of these implementation strategies is called an implementation revision. Each implementation revision contains the data files and reports that are created based on a specific set of implementation strategies.

This method allows you to vary how your design is implemented in order to achieve your design objectives. For example, you can maximize speed and density in your design by controlling the implementation settings or by targeting a different device family better suited for your design.

Note: If you are using an HDL flow, it is strongly recommended that you create a new synthesis netlist when you change FPGA or CPLD families. This ensures that the tools make the best use of the target device.

When you create a new revision either manually or automatically, the data from the “last” revision is copied to the new revision by default. The “last” revision is bottommost in the Design Manager project view. You can copy data from other revisions by setting options in the Copy Persistent Data field of the New Version or New Revision dialog box. You can also copy data from other revisions by using the Set Constraint File, Set Guide File(s), and Set Floorplan File(s) menu commands after the revision is created. If you want to change any of the implementation options, use the Options command.

Note: Because you must always have an implementation revision on which to run the tools, at least one revision must always exist for each version in the Design Manager. If only one revision exists inside a version, you can only delete the revision by deleting the version.

Design Management Basic Procedure

The typical procedure for managing a design is as follows.

1. In your design entry tool, create a design.
   
   
2. In your design entry tool, output your design as an EDF, EDIF, EDN, SEDIF, PLD, SXNF, XNF, or XTF file. The PLD format is supported for CPLDs only.
   
   
3. In the Design Manager, open an existing project or create a new project in which to implement your logic design.
   
   
4. Implement your design.
   
   
   • If necessary, choose a different target device in which to implement your design. The initial target device is specified in the input design or when you create a new implementation revision.
     
     
   • Select implementation, simulation, and configuration options. You can use the default settings, an existing set of options, or set new options.
     
     
   • Run your design implementation and create timing simulation files and a device programming file.
     
     
5. Review your design reports to verify that your design fits within the target device and that your timing requirements are met.
   
   
6. If your design requirements are not met, you can do any of the following and process your design again.
   
   
   • Change your logic design.
     
     
   • Choose a different target device, package, or speed grade.
     
     
   • Define a different set of implementation, simulation, or configuration options.