Flow Engine Fundamentals

The Flow Engine allows you to easily process and control the implementation of your design.

Design Implementation

When you process your design, the Flow Engine translates the design file into the Xilinx Native Generic Database (NGD) format. The Flow Engine then implements your design and generates bitstream data.

The Flow Engine allows you to control the implementation of your design in different ways. For example, if you are new to Xilinx software or want to quickly check your design, you can run the Flow Engine automatically using the Design Manger Design Implement command. However, if you are an experienced user, you can open the Flow Engine from the Design Manger Tools menu and use the interactive Flow Engine to execute steps separately. You can also fine tune your design by modifying your implementation, simulation, and configuration options. You can access these options through the Design Manager's Design Options command or the Flow Engine's Setup Options command. Use the Design Manager Options command with the automatic Flow Engine and the Flow Engine Options command with the interactive Flow Engine.

If you use the interactive Flow Engine, you can control how far to process your design using the Flow Engine's Setup Stop After command. In the Stop After dialog box, select a step as your target break point. For example, if you want to map, place, and route your design but not create device programming file, select Stop After Place&Route. A stop sign indicates where the process flow will stop.

Following are the steps run by the Flow Engine.

Translate

During this step, the Flow Engine merges all of the input netlists. You can control aspects of the Translate step by setting implementation options using the Options command from the Design Manager or Flow Engine. The Flow Engine accomplishes this step by running NGDBuild, which is described in the “NGDBuild” chapter of the Development System Reference Guide.

Map (FPGA)

During this step, the Flow Engine maps a logical design to a Xilinx FPGA. The input is an NGD file, which contains a logical description of the design and macro library (NMC) files. The Flow Engine first performs a logical Design Rule Check (DRC) on the design in the NGD file. It then maps the logic to the components in the target Xilinx FPGA. The output design is an Native Circuit Description (NCD) file that physically represents the design mapped to the components in the Xilinx FPGA. You can control aspects of the Map step by setting implementation options using the Options command from the Design Manager or Flow Engine. The Flow Engine accomplishes the Map step by running the MAP program, which is described in the “MAP - The Technology Mapper” chapter of the Development System Reference Guide.

Place&Route (FPGA)

During this step, the Flow Engine takes the NCD file produced during Map and places and routes the design to produce a routed NCD file. The output NCD file can also act as a guide file if you place and route the design again. You can control aspects of the Place and Route step by setting implementation options using the Options command from the Design Manager or Flow Engine. To accomplish this step, the Flow Engine runs the PAR program, which is described in the “PAR - Place and Route” chapter of the Development System Reference Guide.

Fit (CPLD)

During Fit, the Flow Engine launches the CPLD Fitter to minimize and collapse the combinational logic of your design so that it requires the least number of macrocell and product term resources. It also partitions and maps your design to fit within the architecture of the CPLD. You can control aspects of this step by setting implementation options using the Options command from the Design Manger or Flow Engine.

Timing (Sim)

The Flow Engine runs this step to produce timing simulation data. The data that is produced depends on the simulation options you set using the Options command from the Design Manager or Flow Engine. To accomplish this step, the Flow Engine runs NGDAnno and one of the following tools, all of which are described in the Development System Reference Guide.

• NGD2EDIF
  
  
• NGD2VER
  
  
• NGD2VHDL
  
  

Configure (FPGA)

After the design has been completely routed, the Flow Engine configures the device so that it can execute the desired function. Using a fully routed NCD file as input, it produces a configuration bitstream, a binary file with a .bit extension. The BIT file contains all of the configuration information from the NCD file defining the internal logic and interconnections of the FPGA, plus device-specific information from other files associated with the target device. The binary data in the BIT file can then be downloaded into the FPGA's memory cells, or it can be used to create a PROM file. You can control aspects of this step by setting configuration options using the Options command from the Design Manager or Flow Engine. The Flow Engine accomplishes this step by running BitGen, which is described in the “BitGen” chapter of the Development System Reference Guide.

Bitstream (CPLD)

During this step, the Flow Engine produces a JED programming file. The JTAG Programmer uses this file to configure CPLD devices. You can control aspects of this step by setting implementation options using the Options command from the Design Manager or Flow Engine.

Note: For more information on setting implementation, simulation, and configuration options, see the “Specifying Implementation Flow Options” section of the “Using the Design Manager and Flow Engine” chapter.

Smart Flow Engine

When the Flow Engine is first invoked, it automatically looks for changes made to certain files. If the Flow Engine detects changes, it restarts the flow for the implementation revision as follows. This feature is called the Smart Flow Engine.

• If a previously set target break point has already been reached at the time you launch the Flow Engine, the Smart Flow Engine removes the break point and implements the next process in the flow.
  
  
• If any of the following changes are made, the Smart Flow Engine determines which process to rerun.
  
  
  • Changes to implementation flow options from the Options dialog box or Template Manager
    
    
  • Changes to design, constraints, guide, or output files
    
    The following table shows which flow process the Flow Engine reruns if you make changes to a particular file.
    
    

    Table 1_1 Smart Flow Engine Change Detection

    File Changed	Process Rerun
    design_name.ucf	Translate
    design_name.ngd design_name.mfp	Map (FPGA)
    map.ncd guide.ncd	Place&Route (FPGA)
    design_name.ngd design_name.gyd	Fit (CPLD)
    design_name.ncd	Timing (Sim) (FPGA)
    design_name.vm6	Timing (Sim) (CPLD)
    design_name.ncd	Configure (FPGA)
    design_name.vm6	Bitstream (CPLD)

    
    
    
    

The Smart Flow Engine notifies the Design Manager of the state and status of your implementation revision and the Design Manager updates the information in the main window.

Note: The Flow Engine checks for changes related to successfully completed processes. If a process did not complete successfully, the Flow Engine does not look for changes related to this process but automatically restarts the flow at this process or, if appropriate, at a previous process. If the Flow Engine is already open and you want to check for changes, use the Setup Update Flow command.