Generating Pin Locking Constraints

You can generate pin locking constraints in your UCF file for use with other Xilinx implementation tools. Pinout information is taken from a placed NCD file for FPGAs or a fitted GYD file for CPLDs.

1. In the Design Manager, select Design Lock Pins.
   
   
2. In the confirmation dialog box, click Yes.
   
   Pin locking constraints that you created with this command are added to your UCF file in the PINLOCK section.
   
   
3. After the constraints are added, the dialog box shown in the following figure appears. Click View Lock Pins Report to view the report.
   
   

   Figure 3.18 Lock Pins Status Dialog Box

   You can view the pinouts using the Constraints Editor. See the Constraints Editor Guide for more information.
   
   

   Note: If you want to view the report after you have dismissed the Lock Pins Status dialog box, use the Utilities Lock Pins Report from the Design Manager.