Producing Timing Reports

You can generate timing reports after you implement your design using the Produce Timing Reports command. You can use this command if Map for FPGAs or Fit for CPLDs has completed successfully. The timing report created is based on the state of your design when you run the command.

Note: If you select the appropriate options in the Timing Reports tab of the Implementation Options dialog box before you implement your design, the software automatically generates timing reports with the Map and Place&Route steps. See the “Specifying Implementation Flow Options” section for information on making settings in the Implementation Options dialog box.

1. Select Utilities Produce Timing Reports.
   
   The following dialog box appears if you are targeting an FPGA.
   
   

   Figure 3.16 Produce Timing Reports Dialog Box (FPGA)

   The following dialog box appears if you are targeting a CPLD.
   
   

   Figure 3.17 Produce Timing Reports Dialog Box (CPLD)

2. Select a timing report format. For information on these formats, see the “Produce Timing Report Dialog Box (FPGA)” or “Produce Timing Report Dialog Box (CPLD)” section of the “Menu Commands” chapter.
   
   The timing report is created and placed in the Report Browser. See the “Viewing Reports” section for information on viewing reports.