XC4000 Configuration Options

Design Manager/Flow Engine GuideChapter 5: Implementation Flow Options

XC4000 Configuration Options

Click the Configuration, Startup, Readback, Tie, or Advanced tab to access the different options within the Configuration Options dialog box. These options affect the Configure step in the implementation flow. Use the different tabs of this dialog box to set the options described in the following sections.

Click OK to accept the options, click Cancel to exit the dialog box without changing any settings, click Default to set the default options, or click Help to obtain online help.

XC4000 Configuration Tab

Use this tab, shown in the following figure, to set the following options.

Figure 5.49 XC4000 Configuration Tab

Configuration Rate

The XC4000 uses an internal configuration clock, CCLK, when configuring in a master mode. The configuration rate option allows you to select the rate for this clock. The following options are available. The default is Slow.

Slow

Select Slow to set the configuration clock rate to 1 MHz (nominal).
Fast

Select Fast to set the configuration clock rate to 8 MHz (nominal).

Threshold Levels (XC4000E and XC4000EX Only)

The Threshold Levels group box contains the following options.

Note: These options are supported for the XC4000E and XC4000EX subfamilies only.

Inputs

Specify one of the following input options. The default is Read from Design.
- TTL
  
  Select TTL to specify TTL-compatible inputs.
- CMOS
  
  Select CMOS to specify CMOS-compatible inputs.
- Read from Design
  
  Select Read from Design to specify the TTL/CMOS input level included in the physical contraints (PCF) file.
Outputs

Specify one of the following output options. The default is Read from Design.
- TTL
  
  Select TTL to specify TTL-compatible output.
- CMOS
  
  Select CMOS to specify CMOS-compatible outputs.
- Read from Design
  
  Select Read from Design to specify the TTL/CMOS output level included in the PCF file.

Configuration Pins

The Configuration Pins group box contains the following options.

TDO

The TDO pin can be used as tristatable output pin. The value of the pull-up and pull-down resistors is 50 to 100 kilohms. The following options are available. The default is Float.
- Float
  
  Select Float to disable both the pull-up resistor and pull-down resistor on the TDO pin.
- PullUp
  
  Select PullUp to enable a pull-up on the TDO pin.
- PullDown
  
  Select PullDown to enable a pull-down on the TDO pin.
M0

The M0 pin is used to determine the configuration mode. The value of the pull-up and pull-down resistors is 50 to 100 kilohms. The following options are available. The default is Float.
- Float
  
  Select Float to disable both the pull-up resistor and pull-down resistor on the M0 pin.
- PullUp
  
  Select PullUp to enable a pull-up on the M0 pin.
- PullDown
  
  Select PullDown to enable a pull-down on the M0 pin.
M1

The M1 pin can be used as tristatable output pin. The value of the pull-up and pull-down resistors is 50 to 100 kilohms. The following options are available. The default is Float.
- Float
  
  Select Float to disable both the pull-up resistor and pull-down resistor on the M1 pin.
- PullUp
  
  Select PullUp to enable a pull-up on the M1 pin.
- PullDown
  
  Select PullDown to enable a pull-down on the M1 pin.
M2

The M2 pin is used to determine the configuration mode. The value of the pull-up and pull-down resistors is 50 to 100 kilohms. The following options are available. The default is Float.
- Float
  
  Select Float to disable both the pull-up resistor and pull-down resistor on the M2 pin.
- PullUp
  
  Select PullUp to enable a pull-up on the M2 pin.
- PullDown
  
  Select PullDown to enable a pull-down on the M2 pin.
Done

The DONE pin configures an open-drain driver that requires a pull-up resistor to indicate the end of the configuration. The value of the pull-up resistor is 2 to 8 kilohms. The following options are available. The default is PullUp.
- Float
  
  Select Float to disable the pull-up resistor on the DONE pin. If you select this option, be sure you have connected an external pull-up resistor to this pin.
- PullUp
  
  Select PullUp to enable an internal pull-up resistor on the DONE pin in XC4000 devices. Select this option only if you do not connect an external pull-up resistor to this pin.

XC4000XLA and XC4000XV Only

This group box contains the following options.

5V Tolerant I/Os

This option allows a 3.3 V device circuitry to tolerate 5 V operation. For any device that operates on a mixed circuit environment with 3.3V and 5V, use this option. For any circuitry that operates exclusively on 3.3 V, such as in a laptop computer, turn this option off. Turning off this option reduces power consumption. By default, this option is on.

Note: Enabling this option allows the device's clamping diodes to clamp ringing transients back to the 3.3 V supply rail. A clamping diode is connected from each output to VCC. This option affects all I/O pins.
Enable EXPRESS Mode

This option enables express mode configuration. In this mode, configuration data is presented to the device in parallel format, and each new byte is clocked into the target device with every rising edge of the CCLK. This mode is eight times as fast as other configuration modes because data is processed at the rate of one byte per CCLK rather than one bit per CCLK. By default, this option is off.
Enable Configuration Through the JTAG Port

This option allows BSCAN-based configuration after the device is successfully configured. This feature allows board testing without the risk of reconfiguring XLA devices by toggling the TCK/TMS/TDI/TDO lines. By default, this option is on.
Enable the Status Bits to be Read Through the JTAG Port

This option allows direct sensing of the DONE configuration state after performing a BSCAN-based configuration. This allows you to determine if a BSCAN-based configuration was successful. By default, this option is off.

Perform CRC During Configuration

This option enables Cyclic Redundancy Checking (CRC) error checking during configuration. If enabled, the software calculates a running CRC and inserts a unique four-bit partial check at the end of each data frame in the configuration bitstream. This allows the device to perform a CRC check on the bitstream during the configuration process. If disabled, the device performs a simple check for the 0110 pattern at the end of each frame in the configuration data. By default, this option is on.

Produce ASCII Configuration File

This option creates a rawbits (RBT) file in addition to the binary BIT file. The RBT file is a text file that contains ASCII 1s and 0s. These characters represent the actual bits in the configuration bitstream that are downloaded to the FPGA. By default, this option is off.

XC4000 Startup Tab

Use this tab, shown in the following figure, to set the configuration startup options.

Figure 5.50 XC4000 Startup Tab

The XC4000 Startup tab is identical to the tab described in the “Spartan Startup Tab” section.

XC4000 Readback Tab

Use this tab, shown in the following figure, to set the configuration readback options.

Figure 5.51 XC4000 Readback Tab

The XC4000 Readback tab is identical to the tab described in the “Spartan Readback Tab” section.

XC4000 Tie Tab

Use this tab, shown in the following figure, to set the tie options.

Figure 5.52 XC4000 Tie Tab

The X4000 Tie tab is identical to the tab described in the “Spartan Tie Tab” section.

XC4000 Advanced Tab

Use this tab, shown in the following figure, to set the following options.

Figure 5.53 XC4000 Advanced Tab

XC4000EX/XL Only - Configuration Address Lines

Use the Configuration Address Lines option to set the number of address lines that will be used by the FPGA during device configuration. Address lines are used to address data from a parallel PROM or flash memory device. Select either 18 or 22. If you choose 22, four extra device pins are activated as configuration address lines. The default is 18.

This option only applies to master parallel mode configuration. You must set this option in addition to setting the mode pins. Refer to the Programmable Logic Data Book for more information on address lines and master parallel mode configuration.