XC5200 Simulation Options

Click the General, VHDL/Verilog, or EDIF tab to access the different options within the Simulation Options dialog box. These options affect the timing simulation data produced during the Timing (Sim) step of the implementation flow. Use the different tabs of this dialog box to set the options described in the following sections.

Click OK to accept the options, click Cancel to exit the dialog box without changing any settings, click Default to set the default options, or click Help to obtain online help.

XC5200 General Tab

Use this tab, shown in the following figure, to set the general simulation options.

Figure 5.58 XC5200 General Tab

The XC5200 General tab is identical to the tab described in the “Spartan General Tab” section.

XC5200 VHDL/Verilog Tab

Use this tab, shown in the following figure, to set the VHDL or Verilog options.

Figure 5.59 XC5200 VHDL/Verilog Tab

The XC5200 VHDL/Verilog tab is identical to the tab described in the “Spartan VHDL/Verilog Tab” section.

XC5200 EDIF Tab

Use this tab, shown in the following figure, to set the EDIF options.

Figure 5.60 XC5200 EDIF Tab

The XC5200 EDIF tab is identical to the tab described in the “Spartan EDIF Tab” section.