Spartan Simulation Options

Click the General, VHDL/Verilog, or EDIF tab to access the different options within the Simulation Options dialog box. These options affect the timing simulation data produced during the Timing (Sim) step of the implementation flow. Use the different tabs of this dialog box to set the options described in the following sections.

• “Spartan General Tab”
  
  
• “Spartan VHDL/Verilog Tab”
  
  
• “Spartan EDIF Tab”
  
  

Click OK to accept the options, click Cancel to exit the dialog box without changing any settings, click Default to set the default options, or click Help to obtain online help.

Spartan General Tab

Use this tab, shown in the following figure, to set the following options.

Figure 5.5 Spartan General Tab

Simulation Data Options

Specify the netlist format to use for simulation. The following formats are available.

• EDIF
  
  
• VHDL
  
  
• Verilog
  
  

Correlate Simulation Data to Input Design

Select this option to create a timing simulation netlist that contains the same logic gates and net names as those in the original schematic. Deselect this option to create a timing simulation netlist that contains the same logic gates and net names as those in the optimized implemented netlist.

Simulation Netlist Name

Select this option to specify the name of the output file. This allows you to control the output netlist name to avoid overwriting any files. The default name is time_sim.

Spartan VHDL/Verilog Tab

Use this tab, shown in the following figure, to set the following options.

Figure 5.6 Spartan VHDL/Verilog Tab

Bring Out Global Set/Reset Net as a Port

This option creates a Global Set/Reset port on the top-level simulation module (entity). This port is connected to all flip-flop and latch primitives in the design. Stimulating this port automatically sets or resets every flip-flop and latch to its initial state, as determined in the design. The default name of the Global Set/Reset port depends on the target device family as described in the following table.

Table 5_1 Global Set/Reset Port Information

Use the Port Name field to change the default port name. Specifying the port name allows you to match the port name you used in the front end.

Bring Out Global Tristate Net as a Port

This option creates a global tristate signal (which forces all device outputs to the high-impedance state) as a port on the top-level entity in the output file.

Use the Port Name field to change the default port name. Specifying the port name allows you to match the port name you used in the front end. The default name is GTS.

Note: This option is only used if the global tristate net is not driven.

Generate Test Fixture/Testbench File

This option writes out a Verilog test fixture file or a VHDL testbench file. The test fixture file has a .tv extension. The testbench file has a .tvhd extension.

Include `uselib Directive in the Verilog File

This option writes a library path pointing to the SimPrim library into the output Verilog (.v) file. The path is written as follows, where $XILINX is the location of the Xilinx software.

`uselib dir=$XILINX/verilog/data libext=.vmd

Note: This option is supported for Verilog only.

Generate Pin File

This option writes out a signal-to-pin mapping file. The file has a .pin extension.

Retain Hierarchy in Netlist

This option writes out a Verilog HDL or VHDL file that retains the hierarchy in the original design. The option groups logic based on the original design hierarchy.

Rename Architecture Name to

This option allows you to rename the architecture name generated in your VHDL file. The default architecture name for each entity in the netlist is STRUCTURE.

Spartan EDIF Tab

Use this tab, shown in the following figure, to set the following options.

Figure 5.7 Spartan EDIF Tab

CAE Vendor

Specify the vendor name of your simulation tool in the CAE Vendor drop-down list. This ensures that the correct dialect of EDIF is chosen.

Retain Hierarchy in Netlist

This option writes out a flattened netlist.

Vendor Simulation Library Requirements

The following options apply only if you specify Generic as the CAE Vendor.

• Move Pin-Based Timing Properties to Instances
  
  This option annotates all timing properties to instances.
  
  
• Move External Delays to Buffers on Pins with Internal Delay
  
  This option models certain delays using buffers.