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This chapter explains some of the concepts involved in static timing analysis and how to use the Timing Analyzer to resolve key analysis issues.
Xilinx software tools support two different methodologies of implementing timing analysis. For FPGAs, timing is analyzed through user-defined constraints specified with Timing Analyzer commands and filters. The commands in the Timing Constraints Filters submenu help you customize your analysis. See the “Timing Constraint Filters Submenu (Path Filters Menu)” section of the “Menu Commands” chapter and the XILINX Software Conversion Guide from XACTstep v5.x.x to XACTstep vM1.x.x for more information. CPLDs use system-defined paths for timing analysis. These paths are selected with commands in the Custom Filters submenu. See the “Custom Filters Submenu (Path Filters Menu)” section of the “Menu Commands” chapter for more information on these commands.
This chapter contains these main sections.