Basic Path Types

After you implement your design, you can use the Timing Analyzer to calculate your design's system performance, which is limited by seven basic types of timing paths. Each of these paths goes through a sequence of routing and logic. Because these path delays are affected by the results of the placement and routing that implement the design connectivity, these sequences can vary.

Before you read the Timing Analyzer reports, read the following sections for a description of the basic path types.

Clock to Setup

A clock-to-setup path starts at flip-flop clock inputs and ends at non-clock flip-flop register inputs, D or T, or the receiving flip-flop's t_SU, where that pin has a setup requirement before a clocking signal. Along the way, it propagates through the flip-flop Q output and any number of levels of combinatorial logic. It includes the clock-to-Q delay of a flip-flop, the path delay from that flip-flop to the next flip-flop, and the setup requirement of the next flip-flop.

The clock-to-setup path time is the maximum time required for the data to propagate through the source flip-flop, travel through the logic and routing, and arrive at the destination before the next clock edge occurs. When these flip-flops are clocked by the same clock, the delay on this path is equivalent to the cycle time of the clock. The following figures show a clock-to-setup path which uses the same clock. The “Clock-to-Setup Path (Same Clock) with Timing Diagram” figure also shows a timing diagram describing the path.

Figure 2.1 Clock-to-Setup Path

Figure 2.2 Clock-to-Setup Path (Same Clock) with Timing Diagram

Source and destination flip-flops can be clocked by the same clock on different clock edges. In these cases, the path delay limits the minimum clock high or clock low time as shown in the following two figures.

Figure 2.3 Clock-to-Setup Path (Rising to Falling Edge)

Figure 2.4 Clock-to-Setup Path (Falling to Rising Edge)

If the source and destination are clocked by different clock nets, the clock net on the destination must have a clock period greater than the path delay. The PERIOD constraints allow the Timing Analyzer to use the target flip-flop period for the delay path value. The following figure shows a path of this type.

Figure 2.5 Clock-to-Setup Path (Different Clocks)

Clock-to-setup paths do not propagate from the flip-flop Q output through another flip-flop clock or asynchronous Set and Reset input as shown in the next figure. These paths are also broken at bidirectional pins.

Figure 2.6 Not Propagating Through Asynchronous Set/Reset

Clock to Pad

A clock-to-pad path starts at a clock input of a flip-flop, propagates through the flip-flop Q output and any number of levels of combinatorial logic, and ends at an output pad. It includes the clock-to-Q delay of the flip-flop and the path delay from that flip-flop to the chip output. The clock-to-pad path time is the maximum time required for the data to leave the source flip-flop, travel through logic and routing, and leave the chip. When using the OFFSET constraint, the clock path is also used in the path delay. The following figure illustrates a clock-to-pad path, along with a timing diagram describing the path.

Figure 2.7 Clock-to-Pad Path

Clock-to-pad paths also trace through the enable inputs of tristate controlled pads, as shown in the next figure.

Figure 2.8 Through Tristate Controlled Pads

Clock-to-pad paths do not propagate from the Q output of a flip-flop through the clock of another flip-flop or asynchronous Set and Reset input as shown in the following figure. These paths are also broken at bidirectional pins.

Figure 2.9 Clock-to-Pad Path Broken Through Set/Reset Inputs

Paths Ending at Clock Pin of Flip-Flops

A clock input path starts at a chip input or output. It propagates through any number of levels of combinatorial logic and ends at any clock pin on a flip-flip or latch enable. These paths do not propagate through flip-flops. The clock input path time is the maximum time required for the signal to arrive at the flip-flop clock input. Clock input paths help to determine system-level design timing.

The clock input time is the maximum time only; the Timing Analyzer currently does not calculate minimum clock times.

The next figure shows a clock input path.

Figure 2.10 Paths Ending at Clock Pin of Flip-Flops

Setup to Clock at the Pad

A setup-to-clock-at-the-pad path starts at an input pad, propagates through input buffers and any number of levels of combinatorial logic, and ends at a flip-flop D/T input, which includes the receiving flip-flop's t_SU. This path does not propagate through flip-flops and is also broken at bidirectional pins.

This delay reports t_SU for data inputs relative to global or product term clock inputs. It is calculated according to the following formula for global and product term clocks.

tSU = Pad to Setup - Path Ending at Clock Pin of Flip-Flop

Global clock paths start at global clock pads, propagate through global clock buffers and end at a flip-flop clock pin. Product term clock paths start at input pads, propagate through a single level of logic implemented in a clock product term, and end at the flip-flop clock pin. All three clock-at-the-pad paths are shown in the next figure.

Figure 2.11 Setup-to-Clock-at-the-Pad Path

Clock Pad to Output Pad

A clock-pad-to-output-pad path starts at input pads and trace through all paths that include a flip-flop clock input (except when that path includes a flip-flop asynchronous Set/Reset input) before ending at an output pad. Clock-pad-to-output-pad paths trace through tristate controlled pad enable inputs.

Pad to Pad

A pad-to-pad path starts at an input pad of the chip, propagates through one or more levels of combinatorial logic, and ends at an output pad of the chip. Combinatorial paths also trace through the enable inputs of tristate controlled pads. The pad-to-pad path time is the maximum time required for the data to enter the chip, travel through logic and routing, and leave the chip. It is not controlled or affected by any clock signal. A pad-to-pad path, along with a timing diagram describing the path is displayed in the following figure.

Figure 2.12 Pad-to-Pad Delay

Combinatorial paths are not traced through flip-flops. These paths are also broken at bidirectional pins. A second representation is shown in the next figure.

Figure 2.13 Pad-to-Pad Path

Pad to Setup

A pad-to-setup path starts at an input pad of the chip and ends at a D/T input to a flip-flop, latch, RAM, or the receiving flip-flop's t_SU, wherever there is a setup time against a control signal. Along the way, it propagates through input buffers and any number of combinatorial logic levels. Pad-to-setup paths do not propagate through flip-flops and are broken at bidirectional pins. The pad-to-setup path time is the maximum time required for the data to enter the chip, travel through logic and routing, and arrive at the output before the clock or control signal arrives. A pad-to-setup path and timing diagram is shown in the following figure.

Figure 2.14 Pad-to-Setup Path