Opening a Design

Before you can create a timing report using the Timing Analyzer, load a mapped NCD (FPGA) or a completed placed and routed VM6 (CPLD) design file. The NCD (FPGA) can be mapped, placed, or routed. To open a design for timing analysis, follow these steps.

1. Select File Open Design, or click on the Open Design toolbar button.
   
   
   
   The Open Design dialog box appears, as shown in the “Open Design Dialog Box” figure of the “Menu Commands” chapter.
   
   
2. In the Look in/Directories list box, click on the directory containing the NCD (FPGA) or VM6 (CPLD) file to load.
   
   
3. Under Files of Type/List Files of Type, click on the pull-down the list box and select FPGA Designs (*.ncd) or CPLD Designs (*.vm6).
   
   All the available NCD or VM6 files are displayed in the list box.
   
   
4. Select an NCD or a VM6 file from the list box, or type the name in the field below File Name. (*.ncd appears by default; backspace over the asterisk before typing in the design file name.)
   
   
5. Click OK.
   
   The Timing Analyzer reads your design and device information, processes any timing constraints, and then loads your design. For FPGA designs, the Timing Analyzer also reads the .pcf physical constraints file with the same name as the design file, if one exists in the same directory as the design file (the PCF file contains physical constraints information). The order of the constraints in the PCF file is reflected by the Timing Analyzer.
   
   When your design is loaded, the path name and design file name appear at the top of the Timing Analyzer window.
   
   

You can now create a timing report. Refer to the “Creating Reports” section for instructions on this procedure.