Creating Reports

After you load a design file, you can decide what kind of report you want to generate. This section describes how to create all the reports available in the Timing Analyzer as well as how to save and print them.

With the Find command on the Edit menu, you can search for specific text strings in reports. Directions for this procedure are given in the “Searching for Text in a Report” section.

The Timing Analyzer has default settings that you can change using filters with various commands. Filters modify the scope of generated reports by specifying which paths you want to analyze. For more information, refer to the “Using Path Filtering Commands” section. To view the current settings, refer to the “Viewing Settings” section.

Timing Constraints Analysis

The Timing Constraints Analysis report compares the design's performance to the timing constraints.

There are several ways to generate a Timing Constraints Analysis report. You can use the following toolbar buttons to generate a Timing Constraints Analysis report.

These buttons from left to right are as follows.

• Report Paths in Timing Constraints
  
  
• Report Paths Failing Timing Constraints
  
  
• Report Paths Not Covered by Timing Constraints
  
  

In addition to these buttons the Analyze Timing Constraints submenu contains the following commands.

• Report Paths in Timing Constraints (Analyze Menu)
  
  
• Report Paths Failing Timing Constraints (Analyze Menu)
  
  
• Report Paths Not Covered by Timing Constraints (Analyze Menu)
  
  

To generate a Timing Constraints Analysis report, select one of the three commands in the Analyze Timing Constraints submenu, or click one of the three Timing Constraints Analysis buttons in the toolbar.

This command has an interrupt function when analyzing FPGA designs. A Timing Analysis in Progress dialog box with an Abort button appears.

Clicking the Abort button, the Esc key, or the Enter/Return key aborts the analysis and no report is generated or displayed.

In addition to using the above buttons and commands, you can use the following path filter commands to modify the Timing Constraints Analysis report (See “Using Path Filtering Commands” section for more details).

• Disable Timing Constraints (Path Filters Menu)
  
  
• Include Paths with Nets (Path Filters Menu)
  
  
• Exclude Paths with Nets (Path Filters Menu)
  
  
• Control Path Tracing (Path Filters Menu)
  
  

After processing the design, the Timing Analyzer displays the Timing Constraints Analysis report in a pop-up window. The contents of the window can be saved as a TWR file; see the “Saving a Report” section for the procedure to save a report. Following is an example of a Timing Constraints Analysis report.

-------------------------------------------------------------------------

Timing Analyzer 2.1i

Copyright (c) 1995-1999 Xilinx, Inc.  All rights reserved.



Design file:              testclk.ncd

Physical constraint file: testclk.pcf

Device,speed:             xcv100,-5 (x1_0.71 1.76 Advanced)

Report level:             verbose report, limited to 1 item per constraint

-------------------------------------------------------------------------



=========================================================================

Timing constraint: TS_ck1_i = PERIOD TIMEGRP "ck1_i"  20 nS   HIGH 50.000 % ;

 955 items analyzed, 0 timing errors detected.

 Minimum period is  14.655ns.

-------------------------------------------------------------------------

Slack:     5.345ns path core_inst1/counter1/cont<1> to core_inst1/counter1/cont<9> relative to

          20.000ns delay constraint

Path core_inst1/counter1/cont<1> to core_inst1/counter1/cont<9> contains 12 levels of logic:

Path starting from Comp: CLB_R10C8.S0.CLK (from ck1)

To                   Delay type         Delay(ns)  Physical Resource

                                                   Logical Resource(s)

-------------------------------------------------  --------

CLB_R10C8.S0.YQ      Tcko                  1.203R  core_inst1/counter1/

                                                   cont<1>

                                                   core_inst1/counter1/

                                                   cont_reg<1>

CLB_R11C10.S0.G1     net (fanout=5)        3.073R  core_inst1/counter1/

                                                   cont<1>

CLB_R11C10.S0.COUT   Topcyg                1.545R  core_inst1/counter1/C9/

                                                   C3/C1/O C369

                                                   core_inst1/counter1/

                                                   C9/C3/C1

.

.

.

CLB_R9C10.S1.F1      net (fanout=1)        1.491R  core_inst1/counter1/N362

CLB_R9C10.S1.CLK     Tas                   1.043R  core_inst1/counter1/

                                                   cont<9>

                                                   C303

                                                   core_inst1/counter1/

                                                   cont_reg<9>

-------------------------------------------------

Total (6.638ns logic, 8.017ns route)      14.655ns (to ck1)

      (45.3% logic, 54.7% route)

-------------------------------------------------------------------------

.

.

.

All constraints were met.





Data Sheet report:

-----------------

All values displayed in nanoseconds (ns)



Setup/Hold to clock ck1_i

---------------+------------+------------+

               |  Setup to  |  Hold to   |

Source Pad     | clk (edge) | clk (edge) |

---------------+------------+------------+

res_i          |    6.202(R)|            |

start_i        |    2.213(R)|    0.000(R)|

---------------+------------+------------+



Setup/Hold to clock ck2_i

---------------+------------+------------+

               |  Setup to  |  Hold to   |

Source Pad     | clk (edge) | clk (edge) |

---------------+------------+------------+

res_i          |    5.861(R)|            |

---------------+------------+------------+



Clock ck1_i to Pad

---------------+------------+

               | clk (edge) |

Destination Pad|   to PAD   |

---------------+------------+

out1_o         |   16.691(R)|

---------------+------------+



Clock ck2_i to Pad

---------------+------------+

               | clk (edge) |

Destination Pad|   to PAD   |

---------------+------------+

out2_o         |   14.969(R)|

---------------+------------+



Clock to Setup on destination clock ck1_i

- | Src/Dest| Src/Dest| Src/Dest| Src/Dest|

Source Clock   |Rise/Rise|Fall/Rise|Rise/Fall|Fall/Fall|

---------------+---------+---------+---------+---------+

ck1_i          |   14.655|         |         |         |

---------------+---------+---------+---------+---------+



Clock to Setup on destination clock ck2_i

---------------+---------+---------+---------+---------+

               | Src/Dest| Src/Dest| Src/Dest| Src/Dest|

Source Clock   |Rise/Rise|Fall/Rise|Rise/Fall|Fall/Fall|

---------------+---------+---------+---------+---------+

ck1_i          |   11.886|         |         |         |

ck2_i          |   14.813|         |         |         |

---------------+---------+---------+---------+---------+





Table of Timegroups:

-------------------

TimeGroup ck1_i:

BELs:

 core_inst1/counter1/regist1_reg<0>  core_inst1/counter1/regist1_reg<1>  core_inst1/counter1/regist1_reg<2>  

 core_inst1/counter1/regist1_reg<3>  core_inst1/counter1/regist1_reg<4>  core_inst1/counter1/regist1_reg<5>  

 core_inst1/counter1/regist1_reg<6>  core_inst1/counter1/regist1_reg<7>  core_inst1/counter1/regist1_reg<8>  

 core_inst1/counter1/regist1_reg<9>  core_inst1/counter1/regist0_reg<0>  core_inst1/counter1/regist0_reg<1>  

 core_inst1/counter1/regist0_reg<2>  core_inst1/counter1/regist0_reg<3>  core_inst1/counter1/regist0_reg<4>  

 core_inst1/counter1/regist0_reg<5>  core_inst1/counter1/regist0_reg<6>  core_inst1/counter1/regist0_reg<7>  

 core_inst1/counter1/regist0_reg<8>  core_inst1/counter1/regist0_reg<9>  core_inst1/counter1/cont_reg<0>     

 core_inst1/counter1/cont_reg<1>     core_inst1/counter1/cont_reg<2>     core_inst1/counter1/cont_reg<3>     

 core_inst1/counter1/cont_reg<4>     core_inst1/counter1/cont_reg<5>     core_inst1/counter1/cont_reg<6>     

 core_inst1/counter1/cont_reg<7>     core_inst1/counter1/cont_reg<8>     core_inst1/counter1/cont_reg<9>     



TimeGroup ck2_i:

BELs:

 core_inst2/counter1/regist1_reg<0>  core_inst2/counter1/regist1_reg<1>  core_inst2/counter1/regist1_reg<2>  

 core_inst2/counter1/regist1_reg<3>  core_inst2/counter1/regist1_reg<4>  core_inst2/counter1/regist1_reg<5>  

 core_inst2/counter1/regist1_reg<6>  core_inst2/counter1/regist1_reg<7>  core_inst2/counter1/regist1_reg<8>  

 core_inst2/counter1/regist1_reg<9>  core_inst2/counter1/regist0_reg<0>  core_inst2/counter1/regist0_reg<1>  

 core_inst2/counter1/regist0_reg<2>  core_inst2/counter1/regist0_reg<3>  core_inst2/counter1/regist0_reg<4>  

 core_inst2/counter1/regist0_reg<5>  core_inst2/counter1/regist0_reg<6>  core_inst2/counter1/regist0_reg<7>  

 core_inst2/counter1/regist0_reg<8>  core_inst2/counter1/regist0_reg<9>  core_inst2/counter1/cont_reg<0>     

 core_inst2/counter1/cont_reg<1>     core_inst2/counter1/cont_reg<2>     core_inst2/counter1/cont_reg<3>     

 core_inst2/counter1/cont_reg<4>     core_inst2/counter1/cont_reg<5>     core_inst2/counter1/cont_reg<6>     

 core_inst2/counter1/cont_reg<7>     core_inst2/counter1/cont_reg<8>     core_inst2/counter1/cont_reg<9>     



Timing summary:

---------------



Timing errors: 0  Score: 0



Constraints cover 2184 paths, 0 nets, and 380 connections (100.0% coverage)



Design statistics:

   Minimum period:  14.813ns (Maximum frequency:  67.508MHz)

   Minimum input arrival time before clock:   6.202ns

   Minimum output required time after clock:  16.691ns



Analysis completed Fri Mar 12 12:10:11 1999

------------------------------------------------------------------------

Advanced Design Analysis

The Advanced Design Analysis report provides a set of summary statistics for the paths from the timing requirements submitted for analysis. This report is essentially an error report that displays a summary header for each constraint whether it passes or not and lists paths in error for constraints that are violated.

If the PCF file contains no constraints, the Advanced Design Analysis report creates four basic constraints: PERIOD, OFFSET IN, OFFSET OUT, and PAD TO PAD.

To generate an Advanced Design Analysis report, select Analyze Advanced Design, or click on the Advanced Design button in the toolbar.

This command has an interrupt function when analyzing FPGA designs. A Timing Analysis in Progress dialog box with an Abort button appears.

Clicking the Abort button, the Esc key, or the Enter/Return key aborts the analysis. A report is not generated or displayed.

After processing the design, the Timing Analyzer displays the Advanced Design Analysis report in a pop-up window. The contents of the window can be saved as a TWR file; see the “Saving a Report” section for the procedure to save a report. Following is an example of an FPGA Advanced Design Analysis report.

-------------------------------------------------------------------------

Timing Analyzer 2.1i

Copyright (c) 1995-1999 Xilinx, Inc.  All rights reserved.



Design file:              C:\designs\loop.ncd

Physical constraint file: C:\designs\loop.pcf

Device,speed:             xc4036ex,-3 (x1_0.08 3.7f )

Report level:             error report, limited to 1 item per constraint

-------------------------------------------------------------------------





=========================================================================

Timing constraint: TS01 = MAXDELAY FROM TIMEGRP "FFS" TO TIMEGRP "FFS"

2000.000000 pS PRIORITY 0 ;

 1 item analyzed, 0 timing errors detected.

 Maximum delay is   3.340ns.

-------------------------------------------------------------------------





=========================================================================

Timing constraint: TS02 = MAXDELAY FROM TIMEGRP "PADS" TO TIMEGRP "FFS"

1500.000000 pS PRIORITY 0 ;

 3 items analyzed, 3 timing errors detected.

 Maximum delay is   4.006ns.

-------------------------------------------------------------------------

Slack:    -2.506ns path D to $1N11 relative to

           1.500ns delay constraint



Path D to $1N11 contains 2 levels of logic:

Path starting from Comp: IOB.PAD

To                   Delay type         Delay(ns)  Physical Resource

                                                   Logical Resource(s)

-------------------------------------------------  --------

IOB.I1               Tpid                  1.810R  D

                                                   D

                                                   $1N13

CLB.F1               net (fanout=1)     e  1.066R  $1N13

CLB.K                Tick                  1.130R  $1N11

                                                   $1N15

                                                   $1N11

-------------------------------------------------

Total (2.940ns logic, 1.066ns route)       4.006ns (to $1N19)

      (73.4% logic, 26.6% route)



-------------------------------------------------------------------------



=========================================================================

Timing constraint: TS03 = MAXDELAY FROM TIMEGRP "FFS" TO TIMEGRP "PADS"

2500.000000 pS PRIORITY 0 ;

 1 item analyzed, 1 timing error detected.

 Maximum delay is  10.716ns.

-------------------------------------------------------------------------

Slack:    -8.216ns path $1N11 to OUT relative to

           2.500ns delay constraint



Path $1N11 to OUT contains 2 levels of logic:

Path starting from Comp: CLB.K (from $1N19)

To                   Delay type         Delay(ns)  Physical Resource

                                                   Logical Resource(s)

-------------------------------------------------  --------

CLB.XQ               Tcko                  1.830R  $1N11

                                                   $1N11

IOB.O                net (fanout=2)     e  1.066R  $1N11

IOB.PAD              Tops                  7.820R  OUT

                                                   OUT.OUTBUF

                                                   OUT

-------------------------------------------------

Total (9.650ns logic, 1.066ns route)      10.716ns

      (90.1% logic, 9.9% route)



-------------------------------------------------------------------------





2 constraints not met.





Data Sheet report:

-----------------

All values displayed in nanoseconds (ns)



Setup/Hold to clock ck1_i

---------------+------------+------------+

               |  Setup to  |  Hold to   |

Source Pad     | clk (edge) | clk (edge) |

---------------+------------+------------+

res_i          |    6.202(R)|            |

start_i        |    2.213(R)|    0.000(R)|

---------------+------------+------------+

.

.

.



Table of Timegroups:

-------------------

TimeGroup PADS:

BELs:

 OUT  D    C    CLR  



TimeGroup FFS:

BELs:

 $1N11







Timing summary:

---------------



Timing errors: 4  Score: 15874



Constraints cover 5 paths, 0 nets, and 5 connections (100.0% coverage)





Design statistics:

   Maximum path delay from/to any node:  10.716ns





Analysis completed Wed Mar 3 14:30:42 1999

-------------------------------------------------------------------------

The format of a CPLD Advanced Design Analysis report differs from the FPGA report format, as shown in the following report excerpt.

Design:     tspec1d

Device:     XC9572-7-PC84

Program:    Timing Report Generator Version Internal-M1.0.0a

Date:       Thu Feb 18 10:41:18 1999

Performance Summary:

Worst case Pad to Pad path delay  :     9.0ns (1 macrocell levels)

 (Includes an external input margin of 0.0ns.)

 (Includes an external output margin of 0.0ns.)

Pad `X19' to Pad `Y1'

-------------------------------------------------------------------------

                Combinational Pad to Pad Delays(nsec)

\ From        B    B    C    C    X    X    X    X   X    X    X    X

 \                 B         C    0    1    1    1   1    1    1    1

  \                                         0    1   2    3    4    5

   \

    \

     \

      \

    To \---------------------------------------------------------------

Y1          7.5     7.5         7.5  7.5  7.5  7.5  7.5  7.5  7.5 7.5

Y2                              7.5  7.5  7.5  7.5  7.5  7.5  7.5 7.5

Y3              9.0      9.0

Y4

-------------------------------------------------------------------------

               Combinational Pad to Pad Delays(nsec)

\ From        X    X    X    X    X    X    X    X    X    X    X    X

 \            1    1    1    1    2    3    4    5    6    7    8    9

  \           6    7    8    9

   \

    \

     \

      \

    To \----------------------------------------------------------------

Y1          7.5  7.5  9.0  9.0  7.5  7.5  7.5  7.5  7.5  7.5  7.5 7.5

Y2                              7.5  7.5  7.5  7.5  7.5  7.5  7.5 7.5

Y3

Y4

.

.

.

Path Type Definition: 

Pad to Pad (tPD) -                      Reports pad to pad paths that start 

                                        at input pads and end at output pads. 

                                        Paths are not traced through 

                                        registers. 

Clock Pad to Output Pad (tCO) -         Reports paths that start at input 

                                        pads trace through clock inputs of 

                                        registers and end at output pads. 

                                        Paths are not traced through PRE/CLR 

                                        inputs of registers. 

Setup to Clock at Pad (tSU) -           Reports external setup time of data 

                                        to clock at pad. Data path starts at 

                                        an input pad and end at register D/T 

                                        input. Clock path starts at input pad 

                                        and ends at the register clock input. 

                                        Paths are not traced through 

                                        registers. 

Clock to Setup (tCYC) -                 Register to register cycle time. 

                                        Include source register tCO and 

                                        destination register tSU. 

You can use the following path filtering commands to modify the scope of the Advanced Design Analysis report.

• Include Paths with Nets (Path Filters Menu)
  
  
• Exclude Paths with Nets (Path Filters Menu)
  
  
• Control Path Tracing (Path Filters Menu)
  
  

Custom Analysis

The Custom Analysis report displays a detailed analysis of all specified paths. It contains the worst-case path delays for all paths that are not filtered out.

To generate a Custom Analysis report, select Analyze Custom, or click on the Custom button in the toolbar.

This command has an interrupt function when analyzing FPGA designs. A Timing Analysis in Progress dialog box with an Abort button appears.

Clicking the Abort button, the Esc key, or the Enter/Return key aborts the analysis. A report is neither generated nor displayed.

After processing the design, the Timing Analyzer displays the Custom Analysis report in a pop-up window. The contents of the window can be saved as a TWR file; see the “Saving a Report” section for the procedure to save a report. An example is shown following.

-------------------------------------------------------------------------

Timing Analyzer 2.1i

Copyright (c) 1995-1999 Xilinx, Inc.  All rights reserved.



Design file:              C:\designs\loop.ncd

Device,speed:             xc4036ex,-3 (x1_0.08 3.7f )

Report level:             verbose report, limited to 1 item per constraint

-------------------------------------------------------------------------





=========================================================================

Timing constraint: PATH "PATHFILTERS" = FROM TIMEGRP "SOURCES" TO TIMEGRP

"DESTINATIONS" ; 

 5 items analyzed, 0 timing errors detected.

 Maximum delay is  10.716ns.

-------------------------------------------------------------------------

Delay:    10.716ns $1N11 to OUT



Path $1N11 to OUT contains 2 levels of logic:

Path starting from Comp: CLB.K (from $1N19)

To                   Delay type         Delay(ns)  Physical Resource

                                                   Logical Resource(s)

-------------------------------------------------  --------

CLB.XQ               Tcko                  1.830R  $1N11

                                                   $1N11

IOB.O                net (fanout=2)     e  1.066R  $1N11

IOB.PAD              Tops                  7.820R  OUT

                                                   OUT.OUTBUF

                                                   OUT

-------------------------------------------------

Total (9.650ns logic, 1.066ns route)      10.716ns

      (90.1% logic, 9.9% route)



-------------------------------------------------------------------------





All constraints were met.





Data Sheet report:

-----------------

All values displayed in nanoseconds (ns)



Setup/Hold to clock ck1_i

---------------+------------+------------+

               |  Setup to  |  Hold to   |

Source Pad     | clk (edge) | clk (edge) |

---------------+------------+------------+

res_i          |    6.202(R)|            |

start_i        |    2.213(R)|    0.000(R)|

---------------+------------+------------+

.

.

.





Table of Timegroups:

-------------------

TimeGroup SOURCES:

BELs:

 $1N11  OUT    D      C      CLR    



TimeGroup DESTINATIONS:

BELs:

 $1N11  OUT    D      C      CLR    







Timing summary:

---------------



Timing errors: 0  Score: 0



Constraints cover 5 paths, 0 nets, and 5 connections (100.0% coverage)





Design statistics:

   Maximum path delay from/to any node:  10.716ns





Analysis completed Wed Mar 3 14:31:19 1999

-------------------------------------------------------------------------

You can use the following path filtering commands to modify the scope of the Custom Analysis report.

• Select Sources (Path Filters Menu)
  
  
• Select Destinations (Path Filters Menu)
  
  
• Include Paths with Nets (Path Filters Menu)
  
  
• Exclude Paths with Nets (Path Filters Menu)
  
  
• Control Path Tracing (Path Filters Menu)
  
  

Viewing a Report

When a Timing Analysis report (TWR file) is opened in the Timing Analyzer window, the report window contains three sub-windows, as shown in the following figure.

Figure 4.2 Timing Analyzer Report Window

The report itself is displayed in the lower right window. The upper right window shows what section of the report is currently displayed on the screen. As you scroll through the report, the section name in the upper right window automatically changes.

The window on the left contains a hierarchical display of the headings in the report. Selecting a heading causes the report to scroll immediately to that location. You can click on a box with a plus sign (+) in it to show the sections within that heading.

The size of the three windows can be adjusted as needed.

Saving a Report

Follow this procedure to save a generated report as a file.

1. Make sure the report that you want to save is the active window by clicking on it. The active window has a colored border.
   
   
2. Select File Save, or click the Save button.
   
   
   
   The Timing Analyzer displays the Save As dialog box, illustrated in the “Save As Dialog Box” figure of the “Menu Commands” chapter.
   
   
3. Under List Files of Type, click on the down arrow to display the pull-down list box of available file types. Highlight Timing Analysis Reports (*.twr) to select it. File names of that format appear in the list box below the File Name field.
   
   
4. In the File Name field, type in the name of the file in which to store the report. The .twr extension is added automatically.
   
   If this is the first time you are saving the file, the Timing Analyzer provides a default name corresponding with the type of information contained in the window (timing constraints, clocks, and so forth).
   
   If you want to overwrite an existing file with the new report, click on that file name in the list box, so it appears in the File Name field.
   
   You can use word processor applications to open and edit the report file.
   
   
5. In the Save in field/Directories list box, select the directory in which you want to save the report.
   
   
6. Click OK.
   
   The Save As dialog box closes.
   
   

Searching for Text in a Report

You can use the Find command to search for any text string in the active report window, including normal grammatical symbols like hyphens or underscores. You cannot search for special characters like tabs or hard returns, however.

To search for a text string in a report, do the following.

1. Open or select the report window in which you want to search.
   
   
2. Select Edit Find.
   
   The Find dialog box appears, as shown in the “Find Dialog Box” figure of the “Menu Commands” chapter.
   
   
3. Enter the text string that you want to search for in the Find What field.
   
   
4. You can optionally match the case of the search string by selecting Match Case. Then only instances that have the same case as the text string will be found. By default, case is ignored.
   
   
5. Indicate the search direction, as follows.
   
   
   • Up searches backward from the present location of the cursor to the beginning of the report. Searching stops at the beginning of the report.
     
     
   • Down searches forward from the present location of the cursor to the end of the report. Searching stops at the end of the report. This direction is the default.
     
     
6. Click the Find Next button, the F3 key, or select Edit Find Next to find the next instance of the text string.
   
   
7. Click Cancel to close the Find dialog box.
   
   

Printing a Report

You can send a Timing Analyzer report to your default printer, or you can send it to a printer that you specify.

Note: Print dialog boxes vary between platforms and window operating systems. The procedure in this section is basic; consult your specific system documentation for details.

To send a report to the default printer, follow these instructions.

1. Select File Print, or click the Print button.
   
   
   
   The Timing Analyzer displays the Print dialog box, shown in the “Print Dialog Box” figure of the “Menu Commands” chapter.
   
   
2. If you want to print more than one copy, enter the number of copies that you want to print in the Copies field.
   
   
3. If you want to print a range of pages, enter “From” and “To” pages in the corresponding boxes.
   
   
4. If you want to print to a file, select Print to File.
   
   
5. Click OK.
   
   

Closing a Report

To close a report, use one of the following methods.

Using Menu Commands

Select File Close.

If the report has been previously saved, the window closes. If it has not been saved, the Save As dialog box appears; see the “Saving a Report” section for the procedure to save a report.

Using the Mouse

Make sure the report that you want to close is the active window by clicking on it. The active window will have a colored border.

1. Click on the horizontal bar in the upper left-hand corner of the report pop-up window.
   
   A pop-up menu appears.
   
   
2. Select Close from the menu.
   
   The following prompt box appears.
   
   
   
   
3. Click Yes to save the report window.
   
   The Save As dialog box appears; see the “Saving a Report” section for the procedure to save a report. If you click No, the dialog box and report window both close without saving. If you click Cancel, the dialog box closes and the report window remains open.
   
   

Using the Keyboard

Make sure the report that you want to close is the active window by clicking on it. The active window will have a colored border.

1. Type Ctrl F4 from the keyboard.
   
   The following prompt box appears.
   
   
   
   
2. Click Yes to save the report.
   
   The Save As dialog box appears; see the “Saving a Report” section for the procedure to save a report. If you click No, the dialog box and report window both close without saving. If you click Cancel, the dialog box closes and the report window remains open.
   
   

Opening a Saved Report

You can open a previously saved report to view or print by following these steps.

1. Select File Open.
   
   The Open dialog box appears, as shown in the “Open Dialog Box” figure of the “Menu Commands” chapter.
   
   
2. In the Look in/Directories list box, click on the directory containing the report file to load.
   
   
3. In the List Files of Type field, select Timing Analysis Reports (*.twr) is selected. The default is Timing Analysis Macros (*.xtm).
   
   All the available report files are displayed in the list box (below the File Name field).
   
   
4. Select a report file from the list box, or type the name in the field below File Name after backspacing over the asterisk. If you do not specify a file extension, the Timing Analyzer loads an XTM (macro) file by default.
   
   
5. Click OK.