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The OpenDesign command opens a mapped NCD (FPGA) or a completely placed and routed VM6 (CPLD) design file for timing analysis. The mapped FPGA design can be partially or completely placed, routed, or both.
This command is equivalent to the File 
Open Design menu command.
The syntax of the OpenDesign command is the following.
OpenDesign {design_name.ncd|design_name.vm6}
Design_name is the NCD or VM6 file name, including the path of the directory in which it is located.
This command does not open a report (TWR) file.
You can abbreviate the OpenDesign command syntax as follows.
od design_name.ncd
Following is an example of the OpenDesign command.
opendesign checkers.ncd