Implementation Reports

The implementation reports provide information on logic trimming, logic optimization, timing constraint performance, and I/O pin assignment. To access the reports, select the Reports tab from Project Flow area of the Project Manager. Double click the Implementation Report Files icon to access the implementation reports.

The Implementation Log on the Reports tab is a record of all the implementation processing.

Double click the Implementation Report Files icon to access the Report Browser shown in the following figures. To open a particular report, double click its icon.

Figure 11.10 Report Browser - FPGAs

Figure 11.11 Report Browser - CPLDs

Translation Report

The translation report (.bld) contains warning and error messages from the three translation processes: conversion of the EDIF or XNF style netlist to the Xilinx NGD netlist format, timing specification checks, and logical design rule checks. The report lists the following:

• Missing or untranslatable hierarchical blocks
  
  
• Invalid or incomplete timing constraints
  
  
• Output contention, loadless outputs, and sourceless inputs
  
  

Map Report (FPGAs)

The Map Report (.mrp) contains warning and error messages detailing logic optimization and problems in mapping logic to physical resources. The report lists the following information:

• Erroneously removed logic. Sourceless and loadless signals can cause a whole chain of logic to be removed. Each deleted element is listed with progressive indentation, so the origins of removed logic sections are easily identifiable; their deletion statements are not indented.
  
  
• Logic that has been added or expanded to optimize speed.
  
  
• The Design Summary section lists the number and percentage of used CLBs, IOBs, flip-flops, and latches. It also lists occurrences of architecturally-specific resources like global buffers and boundary scan logic.
  
  

  Note: The Map Report can be very large. To find information, use key word searches. To quickly locate major sections, search for the string `---` , because each section heading is underlined with dashes.

Place and Route Report (FPGAs)

The Place and Route Report (.par) contains the following information.

• The overall placer score which measures the “goodness” of the placement. Lower is better. The score is strongly dependent on the nature of the design and the physical part that is being targeted, so meaningful score comparisons can only be made between iterations of the same design targeted for the same part.
  
  
• The Number of Signals Not Completely Routed should be zero for a completely implemented design. If non-zero, you may be able to improve results by using re-entrant routing or the multi-pass place and route flow.
  
  
• The timing summary at the end of the report details the design's asynchronous delays.
  
  

Pad Report (FPGAs)

The Pad Report lists the design's pinout in three ways.

• Signals are referenced according to pad numbers.
  
  
• Pad numbers are referenced according to signal names.
  
  
• PCF file constraints are listed. This section of the Pad Report can be cut and pasted into the .pcf file after the SCHEMATIC END; statement to preserve the pinout for future design iterations.
  
  

Fitting Report (CPLDs)

The Fitting Report (design_name.rpt) lists summary and detailed information about the logic and I/O pin resources used by the design, including the pinout, error and warning messages, and Boolean equations representing the implemented logic.

Post Layout Timing Report

A timing summary report shows the calculated worst-case timing for the logic paths in your design.