All-Schematic Designs

The following procedure describes how to create a top-level schematic design that contains schematics only, that is, there are no instantiated HDL or State Machine macros.

Creating the Schematic and Generating a Netlist

This section lists the basic steps for creating a schematic and generating a netlist from it.

1. Open the Schematic Editor by selecting the Schematic Editor icon from the Design Entry box on the Project Manager's Flow tab.
   
   
   
   
2. Select Mode Symbols to add components to your new schematic. Select specific components from the SC Symbols window.
   
   
3. Complete your schematic by placing additional components from the Symbol toolbox including I/O ports, nets, buses, labels, and attributes.
   
   
4. Save your schematic by selecting File Save.
   
   

For more information about schematic designs, see the “Schematic Design Entry” chapter or in the Schematic Editor window, select Help Schematic Editor Help Contents.

Performing Functional Simulation

1. Open the Logic Simulator by clicking the Functional Simulation icon in the Simulation box on the Project Manager's Flow tab.
   
   
   
   The design is automatically loaded into the simulator. The Waveform Viewer window displays on top of the Logic Simulator window.
   
   
2. Add signals by selecting Signal Add Signals.
   
   
3. From the Signals Selection portion of the Components Selection for Waveform Viewer window, select the signals that you want to see in the simulator.
   
   
4. Use CTRL-click to select multiple signals. Make sure you add output signals as well as input signals.
   
   
5. Click Add and then Close. The signals are added to the Waveform Viewer in the Logic Simulator screen.
   
   
6. Select Signal Add Stimulators from the Logic Simulator menu. The Stimulator Selection window displays.
   
   
7. In the Stimulator Selection window, create the waveform stimulus by attaching stimulus to the inputs. For more details on how to use the Stimulus Selection window, click the Help button.
   
   
8. After the stimulus has been applied to all inputs, click the Simulation Step icon on the Logic Simulator toolbar to perform a simulation step. The length of the step can be changed in the Simulation Step Value pulldown menu to the right of the Simulation Step box. (If the Simulator window is not open, select View Main Toolbar.)
   
   
   
   
9. Verify that the output waveform is correct. Click the Step button repeatedly to continue simulating.
   
   
10. To save the stimulus for future viewing or reuse, select File Save Waveform. Enter a file name with a .tve extension in the File name box of the Save Waveform window. Click OK.
    
    For more information about saving and loading test vectors, from the Logic Simulator window, select Help Logic Simulator Help Contents. Then select Simulator Reference Working With Waveforms Saving and Loading Waveforms.
    
    

Implementing the Design

1. Click the Implementation icon in the Implementation box on the Project Manager's Flow tab.
   
   
   
   
2. The Implement Design dialog box appears.
   
   
   
   By default, the Implementation targets the device that was previously selected when you created the project. If you want to retarget the design to a different device, use the Implement Design dialog box. If you want to retarget to a new device family, you must first do so in the Foundation Project Manager by selecting File Project Type.
   
   The first time you implement the design, a new version of the design is created and given the default version and revision name shown in the Implement Design dialog box. You can modify the version and revision names as desired.
   
   
3. In the Implement Designs dialog box, select Set. The Settings dialog box appears.
   
   
   
   
4. Specify control files if desired. Click OK to return to the Implement Design dialog box.
   
   
5. In the Implement Design dialog box, select Options. The Options dialog box displays.
   
   
   
   
6. Choose any desired implementation options.
   
   
7. Click OK to return to the Implement Design dialog box.
   
   
8. Click Run to implement your design. The Flow Engine displays the progress of the implementation.
   
   When Implementation is complete, a dialog box appears indicating whether implementation was successful or not.
   
   For more information on the Flow Engine, refer to the “Design Implementation” chapter or select Help Foundation Help Contents Flow Engine.
   
   
9. Select the Reports tab on the Project Manager window and then double click the Implementation Report Files folder. Double click a report icon to review your design reports.
   
   

Creating a New Revision

If you modify the design, then click the Implementation button to re-implement the design after the first revision of a design version has been implemented, the existing revision is overwritten. A warning box appears to allow you to verify the overwrite operation.

You do not access the Implement Design dialog box for subsequent versions/revisions.

If you want to implement a new revision of the design (for any version), you must first create the new revision by selecting Project Create Revision. This accesses the Create Revision dialog box that has the same fields as the Implement Design dialog box. The revision name is automatically entered. Modify the names, control files, and/or options and run the Flow Engine as described previously for the first version/revision.

Creating a New Version

If you want to implement a new version of the design (after the initial implementation), you must first create the new version by selecting Project Create Version. This accesses the Create Version dialog box that has the same fields as the Implement Design dialog box. The version name is automatically entered. Modify the names, control files, and/or options and run the Flow Engine as described previously for the first version/revision.

Editing Implementation Constraints

Constraints are instructions placed on symbols or nets in a schematic (or textual entry file such as VHDL or Verilog). They affect how the logical design is implemented in the target device. Applying constraints helps you to adapt your design's performance to expected worst-case conditions. The user constraint file (.ucf) is an ASCII file that holds timing and location constraints. It is read (by NGDBuild) during the translate process in the Flow Engine and is combined with an EDIF or XNF netlist into an NGD file.

In Foundation, a UCF file is automatically associated with a Revision. This UCF file is copied and used as your UCF file within a new revision. You can directly enter constraints in the UCF file or you can use the Xilinx Constraints Editor.

1. The Constraints Editor is a Graphical User Interface (GUI) that you can run after the Translate program to create new constraints in a UCF file. To access the Constraints Editor, select Tools Implementation Constraints Editor from the Project Manager.
   
   The following figure shows an example of the Global tab of the Implementation Constraints Editor.
   
   
   
   
2. Design-specific information is extracted from the design and displayed in device-specific spreadsheets. Click the tabs to access the various spreadsheets.
   
   
3. Right-click on an item in any of the spreadsheets to access a dialog box to edit the value. Use the online help in the dialog boxes to understand and enter specific constraints and options. Or, refer to the online software document, Constraints Editor Guide for detailed information.
   
   The following figure shows an example of the Pad to Setup dialog box accessed when you right click anywhere on the CLR Port row on the Ports tab of the Implementation Constraints Editor and then select Pad to Setup.
   
   
   
   

   Figure 3.2 Implementation Constraints Editor - Ports Tab

4. After you finish editing the constraints, click Save to close the Constraints Editor window
   
   
5. You must rerun the Translate step in the Flow Engine to have your new constraints applied to the design.
   
   
6. Click the Implementation icon on the Project Manager's Flow tab to rerun Translate (and the other phases).
   
   Or, to just rerun the Translate phase, select Tools Implementation Flow Engine. Click Yes to start at the Translate phase when prompted. Then click the Step button at the bottom of the Flow Engine Window window. Exit the Flow Engine when the Translate phase is Completed.
   
   

Verifying the Design

Performing a Static Timing Analysis (Optional)

1. Click the Timing Analyzer icon in the Verification box on the Project Manager's Flow tab.
   
   
   
   
2. Perform a static timing analysis on mapped or placed and routed designs for FPGAs.
   
   

For FPGAs, you can perform a post-MAP or post-place timing analysis to obtain rough timing information before routing delays are added. You can also perform a post-implementation timing analysis on CPLDs after a design has been implemented using the CPLD fitter.

For details on how to use the Timing Analyzer, select Help Foundation Help Contents Timing Analyzer.

Performing a Timing Simulation

1. Open the Timing Simulator by clicking the Timing Simulation icon in the Verification box on the Project Managers's Flow tab. The implementation timing netlist will be loaded into the simulator.
   
   
   
   
2. The Waveform Viewer window displays on top of the Logic Simulator window.
   
   Refer to the “Performing Functional Simulation” section for instructions on simulating the design. (The operation of the simulator is the same for functional and timing simulation.)
   
   
3. If you have already saved test vectors (for instance, in the functional simulation), you may load these vectors into the timing simulator by selecting File Load Waveform.
   
   

Programming the Device

1. Click the Device Programming icon in the Programming box on the Project Manager's Flow tab.
   
   
   
   
2. From the Select Program box, choose the Hardware Debugger, the PROM File Formatter, or the JTAG Programmer.
   
   For CPLD designs, you must use the JTAG Programmer. For instructions, select Help Foundation Help Contents JTAG Programmer.
   
   For FPGA designs, use the JTAG Programmer, Hardware Debugger, or PROM File Formatter. For instructions, select Help Foundation Help Contents Advanced Tools and then select the desired tool.