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Foundation Series 2.1i User Guide
Chapter 3: Design Methodologies - Schematic Flow

Finite State Machine (FSM) Designs

The FSM Editor allows you to specify functionality using the "bubble state diagram" concept. Once you have described the state machine (or machines) using the FSM Editor's available graphics objects, the State Editor generates behavioral VHDL, Verilog, or ABEL code (depending on which language type was selected when the state diagram was begun). This code can then be synthesized to a gate-level netlist.

A schematic project can have a top-level ABEL design created with a text editor or with the FSM Editor. (Top-level ABEL designs are not recommended for FPGA projects.)

The Finite State Machine Editor can also generate ABEL, VHDL, or Verilog macros that can be included in top-level schematic or ABEL designs.

This section describes using the FSM Editor to produce a top-level ABEL design for a Schematic Flow project. It also includes information on using the FSM Editor to produce underlying ABEL, VHDL, or Verilog macros for inclusion into a top-level design in a Schematic Flow project.

Creating a State Editor Design

  1. Click the FSM Editor icon in the Design Entry box on the Project Manager's Flow tab.



  2. When the State Editor window appears, you may select an existing FSM macro or create a new one. The following steps describe creating a new FSM macro with the Design Wizard.

  3. From the Design Wizard window, select Next.

  4. From the Design Wizard - Language window, choose VHDL, Verilog, or ABEL (Schematic Flow only) and select Next.

  5. In the Design Wizard - Name window, enter a name for your design. Select Next.

  6. Define your ports in the Design Wizard-Ports window. Select Next.

  7. In the Design Wizards - Machines window, select the number of State Machines that you want. Click Finish. The Wizard creates the ports and gives you a template in which you can enter your macro design.

  8. Define the states in the FSM Editor.

Defining States

  1. From the State Editor window, select FSM State or click on the State button in the vertical toolbar.

  2. Place the state bubble. The default state name is S1.

  3. Click on the state name to select it, then click again to edit the text.

  4. Type the desired state name.

  5. Click on the state bubble to select it. Click and drag the small squares to change the size and shape of the bubble. When the state bubble is large enough to hold the name, click and drag the state name to center it in the bubble.

  6. Repeat steps 1-4 to create new states.

    To ensure that the state machine powers up in the correct state, you must define an asynchronous reset condition. This reset will not be connected in the schematic, but its presence directs the compiler to define the state encoding so that the machine will power up in the correct state.

  7. Select FSM Reset, or click Reset in the vertical toolbar.

  8. Place the reset symbol in the state diagram. Click inside a state bubble to define this as the reset state.

  9. To define the reset as asynchronous, right-click on the reset symbol and select Asynchronous.

  10. Define the transition, conditions, and actions for the state diagram.

  11. When you have completed the state diagram, select File Save.

Defining Transitions, Conditions, and Actions

Transitions define the changes from one state to another. They are drawn as arrows between state bubbles.

If there is more than one transition leaving a state, you must associate a condition with each transition. A condition is a Boolean expression. When the condition is true, the machine moves along the transition arrow.

Actions are HDL statements that are used to make assignments to output ports or internal signals. Actions can be executed at several points in the state diagram. The most commonly used actions are state actions and transition actions. State actions are executed when the machine is in the associated state. Transition actions are executed when the machine goes through the associated transition.

Adding a Top-Level ABEL Design to the Project

ABEL FSM designs can be used as top-level designs in a Schematic Flow project. After you have created an ABEL macro using the FSM Editor, perform the following steps to add the design to the project.

  1. From the State Editor window, select File Save to save the ABEL state diagram.

  2. Select Project Add to project.

  3. Select Synthesis Synthesize.

To complete the design, read the following sections in the order listed: