HDL Designs with State Machines

This section explains how to create a state machine and add it into a HDL Flow project.

The Files tab in the Hierarchy Browser displays the state machine name. HDL code is automatically generated from the FSM diagram. The module (VHDL) or entity (Verilog) name is automatically added to the top-level selection list.

Creating a State Machine Macro

1. Open the State Editor by clicking the FSM icon in the Design Entry box on the Project Manager's Flow tab.
   
   
2. Select Use the HDL Design Wizard. Click OK.
   
   
3. From the Design Wizard window, select Next.
   
   
4. From the Design Wizard - Language window, choose VHDL or Verilog and select Next.
   
   
5. In the Design Wizard - Name window, enter a name for your macro. Select Next.
   
   
6. Define your ports in the Design Wizard-Ports window. Select Next.
   
   
7. In the Design Wizards - Machines window, select the number of state machines that you want. Click Finish. The Wizard creates the ports and gives you a template in which you can enter your macro design.
   
   
8. Complete the design for your FSM in the State Editor.
   
   
9. Add the macro to the project by selecting Project Add to Project from the Project Manager.
   
   

You will see the FSM module listed in the Files tab of the Project Manager.

Following is an example of VHDL code (my_fsm.vhd) generated from the State Editor for a state machine macro.

library IEEE;

use IEEE.std_logic_1164.all;

use IEEE.std_logic_arith.all;

use IEEE.std_logic_unsigned.all;

entity my_fsm is

  port (clk: in STD_LOGIC;

        in_a: in STD_LOGIC;

        in_b: in STD_LOGIC;

        in_c: in STD_LOGIC;

        reset: in STD_LOGIC;

        out_a: out STD_LOGIC;

        out_b: out STD_LOGIC;

        out_c: out STD_LOGIC);

end;

architecture my_fsm_arch of my_fsm is

-- SYMBOLIC ENCODED state machine: Sreg0

type Sreg0_type is (S1, S2, S3);

signal Sreg0: Sreg0_type;

begin

--concurrent signal assignments

--diagram ACTIONS

process (clk)

begin

if clk'event and clk = '1' then

 if reset='1' then

  Sreg0 <= S1;

 else

 case Sreg0 is

  when S1 =>

   if in_a = '1' then

    Sreg0 <= S2;

   end if;

  when S2 =>

   if in_b = '1' then

    Sreg0 <= S3;

   end if;

  when S3 =>

   if in_c = '1' then

    Sreg0 <= S1;

   end if;

  when others =>

   null;

 end case;

 end if;

end if;

end process;

-- signal assignment statements for combinatorial

-- outputs

out_c <= '0' when (Sreg0 = S2) else

         '0' when (Sreg0 = S3) else

         '1';

out_a <= '1' when (Sreg0 = S2) else

         '0' when (Sreg0 = S3) else

         '0';

out_b <= '0' when (Sreg0 = S2) else

         '1' when (Sreg0 = S3) else

         '0';

end my_fsm_arch;

For more information about creating state machine modules, refer to the“State Machine Designs” chapter. Or, select Help Foundation Help Contents and then Click State Editor.