VHDL Construct Support

A construct can be fully supported, ignored, or unsupported. Ignored and unsupported constructs are defined as follows.

• Ignored means that the construct is allowed in the VHDL source but is ignored by Foundation Express.
  
  
• Unsupported means that the construct is not allowed in the VHDL source and that Foundation Express flags the construct as an error. If errors are found in a VHDL description, the description is not translated (synthesized).
  
  

Constructs are listed in the following order.

• Design units
  
  
• Data types
  
  
• Declarations
  
  
• Specifications
  
  
• Names
  
  
• Operators
  
  
• Operands and expressions
  
  
• Sequential statements
  
  
• Concurrent statements
  
  
• Predefined language environment
  
  

Design Units

• entity
  
  The entity statement part is ignored.
  Generics are supported, but only of type INTEGER.
  Default values for ports are ignored.
  
  
• architecture
  
  Multiple architectures are allowed.
  Global signal interaction between architectures is unsupported.
  
  
• configuration
  
  Configuration declarations and block configurations are supported but only to specify the top-level architecture for a top-level entity.
  
  Attribute specifications, use clauses, component configurations, and nested block configurations are unsupported.
  
  
• package
  
  Packages are fully supported.
  
  
• library
  
  Libraries and separate compilation are supported.
  
  
• subprogram
  
  

Default values for parameters are unsupported. Assigning subprograms to indexes and slices of unconstrained out parameters is unsupported, unless the actual parameter is an identifier.

Subprogram recursion is unsupported if the recursion is not bounded by a static value.

Resolution functions are supported for wired-logic and three-state functions only.

Subprograms can only be declared in packages and in the declaration part of an architecture.

Data Types

• enumeration
  
  Enumeration is fully supported.
  
  
• integer
  
  Infinite-precision arithmetic is unsupported.
  
  Integer types are automatically converted to bit vectors whose width is as small as possible to accommodate all possible values of the type's range, either in unsigned binary for nonnegative ranges or in 2's-complement form for ranges that include negative numbers.
  
  
• physical
  
  Physical type declarations are ignored. The use of physical types is ignored in delay specifications.
  
  
• floating
  
  Floating-point type declarations are ignored. The use of floating-point types is unsupported except for floating-point constants used with Express-defined attributes.
  
  
• array
  
  Array ranges and indexes other than integers are unsupported.
  
  Multidimensional arrays are unsupported, but arrays of arrays are supported.
  
  
• record
  
  Record data types are fully supported.
  
  
• access
  
  Access type declarations are ignored, and the use of access types is unsupported.
  
  
• file
  
  File type declarations are ignored, and the use of file types is unsupported.
  
  
• incomplete type declarations
  
  Incomplete type declarations are unsupported.
  
  

Declarations

• constant
  
  Constant declarations are supported except for deferred constant declarations.
  
  
• signal
  
  Register and bus declarations are unsupported. Resolution functions are supported for wired and three-state functions only. Only declarations from a globally static type are supported. Initial values are unsupported.
  
  
• variable
  
  Only declarations from a globally static type are supported. Initial values are unsupported.
  
  
• shared variable
  
  Variable shared by different processes. Shared variables are fully supported.
  
  
• file
  
  File declarations are unsupported.
  
  
• interface
  
  Buffer and linkage are translated to out and inout, respectively.
  
  
• alias
  
  Alias declarations are supported, with the following exceptions.
  
  
  • An alias declaration that lacks a subtype indication
    
    
  • A nonobject alias - such as an alias that refers to a type.
    
    
• component
  
  Only component declarations that list a valid entity name are supported.
  
  
• attribute
  
  

Attribute declarations are fully supported. However, the use of user-defined attributes is unsupported.

Specifications

• attribute
  
  Others and all are unsupported in attribute specifications. User-defined attributes can be specified, but the use of user-defined attributes is unsupported.
  
  
• configuration
  
  Configuration specifications are unsupported.
  
  
• disconnection
  
  Disconnection specifications are unsupported. Attribute declarations are fully supported. However, the use of user-defined attributes is unsupported.
  
  

Names

• simple
  
  Simple names are fully supported.
  
  
• selected
  
  Selected (qualified) names outside of a use clause are unsupported. Overriding the scopes of identifiers is unsupported.
  
  
• operator symbol
  
  Operator symbols are fully supported.
  
  
• indexed
  
  Indexed names are fully supported with one exception. Indexing an unconstrained out parameter in a procedure is unsupported.
  
  
• slice
  
  Slice names are fully supported with one exception. Using a slice of an unconstrained out parameter in a procedure is unsupported unless the actual parameter is an identifier.
  
  
• attribute
  
  Only the following predefined attributes are supported; base, left, right, high, low, range, reverse_range, and length. The event and stable attributes are supported only as described with the wait and if statements. (See the “wait Statements” section of the “Sequential Statements” chapter.) User-defined attribute names are unsupported. The use of attributes with selected names (name.name'attribute) is unsupported.
  
  

Identifiers and Extended Identifiers

An identifier in VHDL is a user-defined name for any of the following: constant, variable, function, signal, entity, port, subprogram, parameter, and instance.

Specifics of Identifiers

The characteristics of identifiers follow.

• They can be composed of letters, digits, and the underscore character ( _ ).
  
  
• Their first character cannot be a number, unless it is an extended identifier (see the example in the next section).
  
  
• They can be of any length.
  
  
• They are case-insensitive.
  
  
• All of their characters are significant.
  
  

Specifics of Extended Identifiers

The characteristics of extended identifiers follow.

• Any of the following can be defined as an extended identifier.
  
  
  • Identifiers that contain special characters
    
    
  • Identifiers that begin with numbers
    
    
  • Identifiers that have the same name as a keyword
    
    
• They start with a backslash character (\), followed by a sequence of characters, followed by another backslash (\).
  
  
• They are case-sensitive.
  
  

The following example shows some extended identifiers.

\a+b\       \3state\

\type\       \(a&b)|c\

For more information about identifiers and extended identifiers, see the “Identifiers” section of the “Expressions” chapter.

Operators

• logical
  
  Logical operators are fully supported.
  
  
• relational
  
  Relational operators are fully supported.
  
  
• addition
  
  Concatenation and arithmetic operators are both fully supported.
  
  
• signing
  
  Signing operators are fully supported.
  
  
• multiplying
  
  The * (multiply) operator is fully supported. The / (division), mod, and rem operators are supported only when both operands are constant or when the right operand is a constant power of 2.
  
  
• miscellaneous
  
  The ** operator is supported only when both operands are constant or when the left operand is 2. The abs operator is fully supported.
  
  
• operator overloading
  
  Operator overloading is fully supported.
  
  
• short-circuit operations
  
  The short-circuit behavior of operators is not supported.
  
  

Shift and Rotate Operators

You can define shift and rotate operators for any one-dimensional array type whose element type is either of the predefined types, BIT or Boolean. The right operand is always of type integer. The type of the result of a shift operator is the same as the type of the left operand. The shift and rotate operators are included in the list of VHDL reserved words in the “VHDL Construct Support” section of this chapter. There is more information about the shift and rotate operators that numeric_std supports in the “Shift and Rotate Operators” section of the “Foundation Express Packages” chapter. The shift operators follow.

• sll
  
  Shift left logical
  
  
• srl
  
  Shift right logical
  
  
• sla
  
  Shift left arithmetic
  
  
• sra
  
  Shift right arithmetic
  
  

The rotate operators follow.

• rol
  
  Rotate left logical
  
  
• ror
  
  Rotate right logical
  
  

The following example illustrates the use of shift and rotate operators.

architecture arch of shft_op is

begin

   a <= "01101";

   q1 <= a sll 1;-- q1 = "11010"

   q2 <= a srl 3;-- q2 = "00001"

   q3 <= a rol 2;-- q3 = "10101"

   q4 <= a ror 1;-- q4 = "10110"

   q5 <= a sla 2;-- q5 = "10100"

   q6 <= a sra 1;-- q6 = "00110"

end;

xnor Operator

You can define the binary logical operator xnor for predefined types BIT and Boolean, as well as for any one-dimensional array type whose element type is BIT or Boolean. The operands must be the same type and length. The result also has the same type and length. The xnor operator is included in the list of VHDL reserved words in the “VHDL Reserved Words” section of this chapter.

a <= "10101";

b <= "11100";

c <= a xnor b; -- c = "10110"

Operands and Expressions

• based literal
  
  Based literals are fully supported.
  
  
• null literal
  
  Null slices, null ranges, and null arrays are unsupported.
  
  
• physical literal
  
  Physical literals are ignored.
  
  
• string
  
  Strings are fully supported.
  
  
• aggregate
  
  The use of types as aggregate choices is unsupported. Record aggregates are supported.
  
  
• function call
  
  Function calls are supported, with one exception: Function conversions on input ports are not supported, because type conversions on formal ports in a connection specification (port map) are not supported.
  
  
• qualified expression
  
  Qualified expressions are fully supported.
  
  
• type conversion
  
  Type conversion is fully supported.
  
  
• allocator
  
  Allocators are unsupported.
  
  
• static expression
  
  Static expressions are fully supported.
  
  
• universal expression
  
  Floating-point expressions are unsupported, except in a Express-recognized attribute definition. Infinite-precision expressions are not supported. Precision is limited to 32 bits; all intermediate results are converted to integer.
  
  

Sequential Statements

• wait
  
  The wait statement is unsupported unless it is one of the following forms.
  
  

  wait until       clock = VALUE;
  
  wait until       clock'event and clock = VALUE;
  
  wait until       not clock'stable and clock = VALUE;

  
  
  VALUE is `0', `1,' or an enumeration literal whose encoding is 0 or 1. A wait statement in this form is interpreted to mean “wait until the falling (VALUE is `0') or rising (VALUE is `1') edge of the signal named clock.”
  
  You cannot use wait statements in subprograms.
  
  
• assert
  
  Assert statements are ignored.
  
  
• report
  
  Report statements are ignored.
  
  
• statement label
  
  Statement labels are ignored.
  
  
• signal
  
  Guarded signal assignment is unsupported. The Transport and after signals are ignored. Multiple waveform elements in signal assignment statements are unsupported.
  
  
• variable
  
  Variable statements are fully supported.
  
  
• procedure call
  
  Type conversion on formal parameters is unsupported. Assignment to single bits of vectored ports is unsupported.
  
  
• if
  
  If statements are fully supported.
  
  
• case
  
  Case statements are fully supported.
  
  
• loop
  
  The for...loops are supported, with two constraints; the loop index range must be globally static, and the loop body must not contain a wait statement. The while loops are supported, but the loop body must contain at least one wait statement. Loop statements with no iteration scheme (infinite loops) are supported, but the loop body must contain at least one wait statement.
  
  
• next
  
  Next statements are fully supported.
  
  
• exit
  
  Exit statements are fully supported.
  
  
• return
  
  Return statements are fully supported.
  
  
• null
  
  Null statements are fully supported.
  
  

Concurrent Statements

• block
  
  Guards on block statements are supported. Ports and generics in block statements are unsupported.
  
  
• process
  
  Sensitivity lists in process statements are ignored.
  
  
• concurrent procedure call
  
  Concurrent procedure call statements are fully supported.
  
  
• concurrent assertion
  
  Concurrent assertion statements are ignored.
  
  
• concurrent signal assignment
  
  The guarded keyword is supported. The transport keyword is ignored. Multiple waveforms are unsupported.
  
  
• component instantiation
  
  Type conversion on the formal port of a connection specification is unsupported.
  
  
• generate
  
  The generate statements are fully supported.
  
  

Predefined Language Environment

• severity_level type
  
  The severity_level type is unsupported.
  
  
• time type
  
  The time type is ignored if time variables and constants are used only in after clauses. In the following two code fragments, both the after clause and TD are ignored.
  
  

  constant TD: time := 1.4 ns;
  
  X <= Y after TD;

  
  
  

  X <= Y after 1.4 ns;

  
  
  
• now function
  
  The now function is unsupported.
  
  
• TEXTIO package
  
  The TEXTIO package is unsupported.
  
  
• predefined attributes
  
  These predefined attributes are supported: base, left, right, high, low, range, reverse_range, ascending, and length. The event and stable attributes are supported only in the if and wait statements, as described in the “wait Statements” section of the “Sequential Statements” chapter.