VHDL Reference GuideChapter 11: VHDL Constructs
VHDL Reserved Words
The following words are reserved for the VHDL language and cannot be used as identifiers.
abs
| if
| reject
|
access
| impure
| rem
|
after
| in
| report
|
alias
| inertial
| return
|
all
| inout
| rol
|
and
| is
| ror
|
architecture
|
|
|
array
| label
| select
|
assert
| library
| severity
|
attribute
| linkage
| shared
|
| literal
| signal
|
begin
| loop
| sla
|
block
|
| sll
|
body
| map
| sra
|
buffer
| mod
| srl
|
bus
|
| subtype
|
| nand
|
|
case
| new
| then
|
component
| next
| to
|
configuration
| nor
| transport
|
constant
| not
| type
|
| null
|
|
disconnect
|
| unaffected
|
downto
| of
| units
|
| on
| until
|
else
| open
| use
|
elsif
| or
|
|
end
| others
| variable
|
entity
| out
| wait
|
exit
|
| when
|
| package
| while
|
file
| port
| with
|
for
| procedure
|
|
function
| process
| xnor
|
|
| xor
|
generate
| range
|
|
generic
| record
|
|
guarded
| register
|
|
