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VHDL Reference Guide
Chapter 2: Design Descriptions

Packages

A package is a collection of declarations that more than one design can use.

You can collect constants, data types, component declarations, and subprograms into a VHDL package that can then be used by more than one design or entity. A package must contain at least one of the following constructs.

Define algorithms that can be called anywhere in a design.

Packages are often sufficiently general so that you can use them in many different designs. For example, the std_logic_1164 package defines data types std_logic and std_logic_vector.

Using a Package

The use statement allows an entity to use the declarations in a package. The supported syntax of the use statement follows.

use LIBRARY_NAME.PACKAGE_NAME.ALL;

A use statement is usually the first statement in a package or entity specification source file.

Note: Foundation Express does not support different packages with the same name when they exist in different libraries. No two packages can have the same name.

Package Structure

Packages have two parts; the declaration and the body.

Holds private information, including local types and subprogram implementations (bodies)

Note: When a package declaration contains subprogram declarations, a corresponding package body must define the subprogram bodies.

Package Declarations

Package declarations collect information that one or more entities in a design need. This information includes data type declarations, signal declarations, subprogram declarations, and component declarations.

Note: Signals declared in packages cannot be shared across entities. If two entities both use a signal from a given package, each entity has its own copy of that signal.

Although you can declare all this information explicitly in each design entity or architecture in a system, it is often easier to declare system information in a separate package. Each design entity in the system can then use the system's package.

The syntax of a package declaration follows.

package package_name is
{ package_declarative_item }
end [ package_name ] ;

The following example shows some sample package declarations.

package EXAMPLE is

  type BYTE is range 0 to 255;
subtype NIBBLE is BYTE range 0 to 15;

  constant BYTE_FF: BYTE := 255;

  signal ADDEND: NIBBLE;

  component BYTE_ADDER
port(A, B: in BYTE;
C: out BYTE;
OVERFLOW: out BOOLEAN);
end component;

  function MY_FUNCTION (A: in BYTE) return BYTE;

end EXAMPLE;

To use the previous example declarations, add a use statement at the beginning of your design description as follows.

use WORK.EXAMPLE.ALL;
entity . . .
architecture . . .

The “Foundation Express Packages” chapter contains more examples of packages and their declarations.

Package Body

A package body includes the following.

But designs or entities that use the package never see this information.

The syntax of a package body follows.

package body package_name is
{ package_body_declarative_item }
end [ package_name ] ;

The “Foundation Express Packages” chapter shows a package declaration and body example that comes with Foundation Express.