|
|
|
|
|
A variable assignment changes the value of a variable. The syntax follows.
target := expression;
target names the variables that receive the value of expression. See the “Assignment Statements and Targets” section of this chapter for a description of variable assignment targets.
Expression determines the assigned value; its type must be compatible with target. See the “Expressions” chapter for further information.
When a variable is assigned a value, the assignment takes place immediately. A variable keeps its assigned value until another assignment takes place.
The following example shows the different effects of variable and signal assignments.
signal S1, S2: BIT;
signal S_OUT : BIT_VECTOR(1 to 8);
. . .
process( S1, S2 )
variable V1, V2: BIT;
begin
V1 := '1'; -- This sets the value of V1
V2 := '1'; -- This sets the value of V2
S1 <= '1'; -- This assignment is the driver for S1
S2 <= '1'; -- This has no effect because of the
-- assignment later in this process
S_OUT(1) <= V1; -- Assigns '1', the value assigned above
S_OUT(2) <= V2; -- Assigns '1', the value assigned above
S_OUT(3) <= S1; -- Assigns '1', the value assigned above
S_OUT(4) <= S2; -- Assigns '0', the value assigned below
V1 := '0'; -- This sets the new value of V1
V2 := '0'; -- This sets the new value of V2
S2 <= '0'; -- This assignment overrides the previous one since it is -- the last assignment to this signal in this process
S_OUT(5) <= V1; -- Assigns '0', the value assigned above
S_OUT(6) <= V2; -- Assigns '0', the value assigned above
S_OUT(7) <= S1; -- Assigns '1', the value assigned above
S_OUT(8) <= S2; -- Assigns '0', the value assigned above
end process;