Signal Assignment Statements

A signal assignment changes the value being driven on a signal by the current process. The syntax follows.

target := expression;

target names the signals that receive the value of expression. See the “Assignment Statements and Targets” section of this chapter for a description of variable assignment targets.

expression determines the assigned value; its type must be compatible with target. For more information about expressions, see the “Expressions” chapter.

Signals and variables behave in different ways when they receive assigned values. The differences lie in the way the two kinds of assignments take effect and how that influences the value Foundation Express reads from either variables or signals.

Variable Assignment

When a variable is assigned a value, the assignment changes the value of the variable from that point on. That value is kept until the variable is assigned a different value.

Signal Assignment

When a signal receives an assigned value, the assignment does not necessarily take effect, because the value of a signal is determined by the processes (or other concurrent statements) that drive the signal.

• If several values are assigned to a given signal in one process, only the last assignment is effective. Even if a signal in a process is assigned, read, and reassigned, the value read (either inside or outside the process) is the last assignment value.
  
  
• If several processes (or other concurrent statements) assign values to one signal, the drivers are wired together. The resulting circuit depends on the expressions and the target technology. The circuit might be invalid, wired AND, wired OR, or a three-state bus. See the “Concurrent Statements” chapter for more information.
  
  

The following example shows the different effects of variable and signal assignments.

signal S1, S2: BIT; 

signal S_OUT:    BIT_VECTOR(1 to 8); 

. . . 

process( S1, S2 ) 

  variable V1, V2: BIT;

begin

  V1 := '1';   -- This sets the value of V1

  V2 := '1';   -- This sets the value of V2

  S1 <= '1';   -- This assignment is the driver for S1

  S2 <= '1';   -- This has no effect because of the

               -- assignment later in this process

  S_OUT(1) <= V1; -- Assigns '1', the value assigned above

  S_OUT(2) <= V2; -- Assigns '1', the value assigned above

  S_OUT(3) <= S1; -- Assigns '1', the value assigned above

  S_OUT(4) <= S2; -- Assigns '0', the value assigned below 

  V1 := '0';   -- This sets the new value of V1

  V2 := '0';   -- This sets the new value of V2

  S2 <= '0';   -- This assignment overrides the previous one since it is                -- the last assignment to this signal in this process

  S_OUT(5) <= V1; -- Assigns '0', the value assigned above

  S_OUT(6) <= V2; -- Assigns '0', the value assigned above

  S_OUT(7) <= S1; -- Assigns '1', the value assigned above

  S_OUT(8) <= S2; -- Assigns '0', the value assigned above

end process;