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Feedback paths and latches result from ambiguities in signal or variable assignments and language supersets or the differences between a VHDL simulator view and the Foundation Express use of VHDL.
Implied combinatorial feedback paths or latches in synthesized logic can occur when a signal or variable in a combinatorial process (one without a wait or if signal'event statement) is not fully specified in the VHDL description. A variable or signal is fully specified when it is assigned under all possible conditions. A variable or signal is not fully specified when a condition exists under which the variable is not assigned.
The following example shows several variables. A, B, and C are fully specified; X is not.
process (COND1)
variable A, B, C, X : BIT;
begin
A <= '0' -- A is hereby fully specified
C <= '0' -- C is hereby fully specified
if (COND1) then
B <= '1'; -- B is assigned when COND1 is TRUE
C <= '1'; -- C is already fully specified
X <= '1'; -- X is assigned when COND1 is TRUE
else
B <= '0'; -- B is assigned when COND1 is FALSE
end if;
-- A is assigned regardless of COND1, so A is fully
-- specified.
-- B is assigned under all branches of if (COND1),
-- that is, both when COND1 is TRUE and when
-- COND1 is FALSE, so B is fully specified.
-- C is assigned regardless of COND1, so C is fully
-- specified. (The second assignment to C does
-- not change this.)
-- X is not assigned under all branches of
-- if (COND1), namely, when COND1 is FALSE,
-- so X is not fully specified.
end process;
The conditions of each if and else statement are considered independent in the previous example. A is considered not fully specified in the following fragment.
if (COND1) then
A <= '1';
end if;
if (not COND1) then
A <= '0';
end if;
A variable or signal that is not fully specified in a combinatorial process is considered conditionally specified. In this case, a flow-through latch is implied. You can conditionally assign a variable, but you cannot read a conditionally specified variable. You can, however, both conditionally assign and read a signal.
If a fully specified variable is read before its assignment statements, combinatorial feedback might exist. For example, the following fragment synthesizes combinatorial feedback for VAL.
process(NEW, LOAD)
variable VAL: BIT;
begin
if (LOAD) then
VAL <= NEW;
else
VAL <= VAL;
end if;
VAL_OUT <= VAL;
end process;
In a combinatorial process, you can ensure that a variable or signal is fully specified by providing an initial (default) assignment to the variable at the beginning of the process. This default assignment assures that the variable is always assigned a value, regardless of conditions. Subsequent assignment statements can override the default. A default assignment is made to variables A and C in the example of fully specified variables.
Another way to ensure that you do not imply combinatorial feedback is to use a sequential process (one with a wait or if signal'event statement). In such a case, variables and signals are registered. The registers break the combinatorial feedback loop.
See the “Register and Three-State Inference” chapter for more information about sequential processes and the conditions under which Foundation Express infers registers and latches.
Some forms of asynchronous behavior are not supported. An example is a circuit description of a one-hot signal generator of the following form.
X <= A nand (not(not(not A)));
You might expect this circuit description to generate three inverters (an inverting delay line) and a NAND gate, but it is optimized to the following.
X <= A nand (not A);
Then, it is optimized to the following.
X <= 1;
c[0] = a[0] & b[0];
for (i = 0; i <= 3; i = i + 1)
c[i] = a[i] & b[i];
The Foundation Express VHDL Analyzer is a full IEEE 1076 VHDL analyzer.
When Foundation Express reads in a VHDL design, it first calls the VHDL Analyzer to check the VHDL source for errors and then translates the VHDL source to an intermediate form for synthesis. If an error is in the VHDL source, you get a VHDL Analyzer message and possibly a VHDL Compiler message.
VHDL Compiler allows globally static objects where only locally static objects are allowed, without issuing an error message.