Don't Care Inference

You can greatly reduce circuit area by using don't care values. To use a don't care value in your design, create an enumerated type for the don't care value.

Don't care values are best used as default assignments to variables. You can assign a don't care value to a variable at the beginning of a module, in the default section of a case statement, or in the else section of an if statement.

The following example shows don't care encoding for a seven-segment LED decoder. Enumeration encoding 'D' represents the don't care state. The figure following the example illustrates the design.

entity CONVERTER is 

  port (BCD: in BIT_VECTOR(3 downto 0);

        LED: out BIT_VECTOR(6 downto 0));

  -- pragma dc_script_begin

  -- set_flatten true

  -- pragma dc_script_end

end CONVERTER;

architecture BEHAVIORAL of CONVERTER is

begin

CONV: process(BCD)

  begin

     case BCD is

       when ”0000” => LED <= ”1111110”;

       when ”0001” => LED <= ”1100000”;

       when ”0010” => LED <= ”1011011”;

       when ”0011” => LED <= ”1110011”;

       when ”0100” => LED <= ”1100101”;

       when ”0101” => LED <= ”0110111”;

       when ”0110” => LED <= ”0111111”;

       when ”0111” => LED <= ”1100010”;

       when ”1000” => LED <= ”1111111”;

       when ”1001” => LED <= ”1110111”;

       when others => LED <= ”0000000”;

     end case;

  end process CONV;

end BEHAVIORAL;

Figure 8.18 Seven-Segment LED Decoder with O LED Default

Using Don't Care Default Values

You do not always want to assign a default value or don't care, although it can be beneficial in some cases, as the seven-segment decoder in the previous example shows.

The reasons for not always defaulting to don't care follow.

• The potential for mismatches between simulation and synthesis is greater.
  
  
• Defaults for variables can hide mistakes in the VHDL code.
  
  For example, you might assign a default don't care value to VAR. If you later assign a value to VAR, expecting VAR to be a don't care value, you might have overlooked an intervening condition under which VAR is assigned.
  
  Therefore, when you assign a value to a variable (or signal) that contains a don't care value, make sure that the variable (or signal) is really a don't care value under those conditions.
  
  

Differences Between Simulation and Synthesis

Don't care values are treated differently in simulation and in synthesis, and there can be a mismatch between the two. To a simulator, a don't care is a distinct value, different from a 1 or a 0. In synthesis, however, a don't care becomes a 0 or a 1 (and the hardware built treats the don't care value as either a 0 or a 1).

Whenever a comparison is made with a variable whose value is don't care, simulation and synthesis can differ. The safest way to use don't care values is to do the following.

• Assign don't care values only to output ports
  
  
• Make sure that the design never reads output ports
  
  

These guidelines guarantee that when you simulate within the scope of the design, the only difference between simulation and synthesis occurs when the simulator defines an output as a don't care.

Note: If you use don't care values internally to a design, expressions compared to don't care (`D') are synthesized as though their values are not equal to `D.'

For example,

if X = 'D' then

...

is synthesized as

if FALSE then

If you use expressions comparing values with `D,' there might be a difference between pre-synthesis and post-synthesis simulation results. For this reason, Foundation Express issues a warning when it synthesizes such comparisons.

Warning: A partial don't-care value was read in routine test line 24 in file 'test.vhdl'  This may cause simulation to disagree with synthesis. (HDL-171)