PPT 슬라이드
- VHDL Code for Multiplier
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity mult is
port (
a,b : in std_logic_vector(3 downto 0);
y : out std_logic_vector(7 downto 0)
);
end mult;
architecture a_mult of mult is
begin
y <= a * b;
end a_mult;