PPT 슬라이드
- Data-types are very important in VHDL. A given data-type define all possible values within its range. Only values within that range may be applied. Each VHDL object (signal, variable, constant) or port must have its type defined when declared.
VHDL is considered to be a strongly “typed” language, connected signals must be of the same type!
The wide range of data-types available provides both flexibility in hardware modeling, and built-in error checking to ensure signal compatibility in large and complex models.