PPT 슬라이드
- Decoder (1) : (Gate Combination)
library ieee;
use ieee.std_logic_1164.all;
entity dec is
port(
a,b,c,d : in std_logic;
y : out std_logic
);
end dec;
architecture a_dec of dec is
signal v3,v4,v6,va : std_logic;
begin
v3 <= (not a) and (not b) and c and d;
v4 <= (not a) and b and (not c) and (not d);
v6 <= (not a) and b and c and (not d);
va <= a and (not b) and c and (not d);
y <= v3 or v4 or v6 or va;
end a_dec;