PPT 슬라이드

Registered Logic

• The “register rich” Xilinx FPGA architecture is excellent for synchronous design, which is the very essence of RTL (Register Transfer Level) level description. There are 2 registers per CLB. Use pipelining as necessary to increase performance

RTL

Behavioral

Logic

CLB 1

CLB 2

5

이전 슬라이드

다음 슬라이드

첫 슬라이드로 이동

그래픽 버전 보기