This glossary describes the basic terminology for the Xilinx/Cadence interface.
A Concept symbol. The format of a body file name is body. version.sheet_number. Example: body.1.1 is version 1, sheet 1 of a Concept symbol.
Verilog parameter definition that must be added to the verilog.v file generated for a LogiBLOX or other non-schematic block to indicate to CONCEPT2XIL that there are no other underlying levels of hierarchy associated with a given block.
A library mapping file pointing to the VAN-compiled Verilog libraries used by CONCEPT2XIL and Concept.
Concept parts file. The file contains physical information about a board level part.
CONCEPT2XIL is the Concept schematic-to-EDIF netlister; it calls several other products, such as HDLConfig, VAN, and SIR2EDIF. CONCEPT2XIL is implemented as a C-shell script. CONCEPT2XIL uses Verilog as an intermediate format. The impact to Xilinx customers is that if a particular design construct is not supported by the Xilinx Verilog libraries, it will not get translated into the EDIF netlist.
Cadence schematic editor used mainly by board level designers.
These four files include startup.concept, cds.lib, global.cmd, and master.local. These files set up your Concept environment. The design.wrk file is also necessary. The use command in the global.cmd file defines the .wrk file name.
Xilinx supplies the Concept Unified Library for use with the Concept schematic design tool. The library contains the Xilinx device families and associated primitives and macros.
A Complex Programmable Logic Device. Also the command “cpld” command that invokes the CPLD fitter. See the CPLD Schematic Design Guide for details.
Electronic Design Interchange Format. An industry-standard netlist format.
EDIF2NGD, a Xilinx translation tool, converts an EDIF 2.0.0 netlist to a Xilinx NGO file. The EDIF file includes the hierarchy of the input schematic. The output NGO file is a binary database describing the design in terms of the components and hierarchy specified in the input design file.
For a description of the EDIF2NGD syntax and options, see the Development System Reference Guide.
A program that ships with the Cadence Concept schematic editor. Genview creates a symbol/body from a Concept schematic, a Verilog netlist, or a user-specified port list. This command is used for the Cadence/LogiBLOX interface for body generation using structural Verilog netlists from the LogiBLOX GUI.
A Concept setup file containing aliases to the Xilinx and Cadence libraries available for your design.
Hardware Description Language. A language that describes circuits in textual code. The two most widely accepted HDLs are VHDL and Verilog. HDL may be used to describe a design in a technology-independent manner using a high-level of abstraction. When used in this way, implementation of a design requires that you first synthesize the design to a gate-level description using a synthesis tool.
Concept's HDLConfig traverses a design's hierarchy and generates a design configuration that points to the cellviews for all the blocks in a design. In the 97A release, HDLConfig reads the global.cmd and hdldirect.dat files.
Cadence Concept methodology for generating simulatable Verilog code directly from schematics. HDL Direct creates a Verilog output file for a schematic design. Required methodology for the Xilinx Development System interface.
A Concept methodology for replicating bodies which involves adding an index range to the value of the PATH property for a given instance. Use this methodology to replicate bodies in designs.
A Concept schematic. The format of a logic drawing file name is logic.version.sheet_number. Example: logic.1.2 is version 1, sheet 2 of a Concept schematic.
LogiBLOX is a Xilinx tool that you can use to create high-level modules for insertion into a schematic or an HDL-based design. LogiBLOX is only supported in standalone mode for the Cadence interface. LogiBLOX is not supported for CPLDs.
MAP is a Xilinx tool that maps the logic in your design to the resources of the FPGA design.
For a description of the MAP syntax and options, see the Development System Reference Guide.
A SCALD library mapping file which list the explicit paths to user libraries. Aliases to each user library are defined in this file. Libraries defined in master.local are available to your design if you include a “master_library” directive in your global.cmd file pointing to master.local.
Mixed Mode refers to designs that contain both schematic and non-schematic blocks.
NGDAnno is Xilinx's back-annotation utility.
For a description of the NGDAnno syntax and options, see the Development System Reference Guide.
NGDBuild, a Xilinx utility, reads a file in EDIF or XNF format, reduces all the components in the design to Xilinx SIMPRIM primitives, runs a logical design rule check on the design, and writes an NGD file as output.
NGD2VER translates your design into a Verilog HDL file that contains a netlist description of the design in terms of a generic, architecture-independent Xilinx simulation primitives. In other words, NGD2VER expands the design in terms of SIMPRIMs. The input files to NGD2VER can be an NGD file used for post-NGDBuild functional simulation or an NGA file that is used for timing simulation.
PAR is Xilinx's place and route tool.
For a description of the PAR syntax and options, see the Development System Reference Guide.
A Concept old-style design methodology describing the logical design of an electronic circuit. SCALD (Structured Computer Aided Logic Design) identifies a language for specification of a logic design around which Concept and its related tools work. The language originated in the Lawrence Livermore Lab.
Concept has been upgraded to work concurrently around an HDL-centric language (that is, Verilog or VHDL) through the HDL Direct tool, while still supporting the SCALD-based flow.
SIR2EDF is Cadence's generic SIR (Structural Intermediate Representation) to EDIF conversion tool. SIR2EDF is one of three subprograms invoked automatically when you invoke CONCEPT2XIL.
A Concept property used for replicating symbols. Not supported in Xilinx Development System Verilog libraries.
A testbench file contains simulation commands that drive a simulation and exercise your design. Typically this file is separate from the actual design netlist. (The terms “testbench” and “test fixture” are used interchangeably.)
The Verilog-XL simulator uses a testbench file to conduct simulation. The Xilinx NGD2VER command -tf option creates a testbench template file that can be copied and edited for use as an actual testbench file. The testbench file contains test vectors to drive a simulation.
Xilinx library standard that emphasizes standardization of component naming and physical appearance of all schematic symbols across all FPGA and CPLD architectures.
VAN is the Cadence Verilog Analyzer. VAN is one of the 3 subprograms invoked automatically when you run CONCEPT2XIL. VAN parses and analyzes Verilog netlists.
An industry-standard HDL developed by Cadence Design Systems. Recognizable as a file with a .v extension.
The term “verilog” is used in four contexts--to refer to an HDL, a command, the Verilog-XL simulator, or Verilog files.
Verilog is an HDL that is used both for design entry and simulation.
To invoke the Verilog-XL simulator, you typically type the command “verilog”.
The simulator is used for RTL/behaviorial functional and timing simulation.
With HDL Direct turned on, Concept generates Verilog files for use with the CONCEPT2XIL command.
Xilinx supplies SIMPRIM-based Verilog simulation libraries for Verilog timing simulation and post-NGDBuild functional simulation. The SIMPRIM library modules are generic, technology-independent. This library is located in the $XILINX/verilog/data tree.
Xilinx supplies the Verilog Unified Simulation Library for post-CONCEPT2XIL HDL Direct functional simulation.
Cadence's Verilog HDL simulator.
SCALD library mapping file for your design. Lists the design blocks in the project directory. Updated by Concept when a new block is created.
XIL2CDS is a Cadence back-end tool that generates data files used to integrate a Xilinx FPGA or CPLD into a board level schematic and board level simulation.
XIL2CDS translates the .PIN, .V, and .SDF files from NGD2VER to two other files: 1) a chips_prt file 2) a body file for the FPGA or CPLD.
The body or symbol can be instantiated into a board level schematic, while the chips_prt file can be used to document information about the FPGA/CPLD.
Ensure that you use the most updated version of the Xilinx .PIN file for ball grid and pin grid arrays. Copy the latest version as follows:
cp $XILINX/cadence/data/xilinx.pga.pin $CDS_INST_DIR/share/libary/xilinx/data/xilinx.pga.pin
The Xilinx Design Manager is Xilinx's design implementation tool. It is invoked by entering dsgnmgr at the UNIX command line.
Xilinx Netlist Format.
