Appendix B

Program Options

This appendix describes Xilinx and Cadence command line programs that pertain to the Xilinx/Cadence interface, providing detailed information about primary programs, such as CONCEPT2XIL, NGD2VER, VERILOG, and XIL2CDS. Xilinx programs are referenced with interbook links.

CONCEPT2XIL

The command line program, CONCEPT2XIL, is the Cadence Concept EDIF netlister. The CONCEPT2XIL program converts the Verilog (.V) file produced by the Concept HDL Direct option to an EDIF file. Xilinx design implementation tools then use this file EDIF file as input. Cadence Design Systems ships and supports CONCEPT2XIL.

Syntax

concept2xil [-sim_only] [-cdslib filename] [-gcmd filename] [-help] [-log filename] [-rundir dirname] -family technology design_name

Options

This subsection describes the CONCEPT2XIL command options.

-cdslib filename

The -cdslib filename option indicates the name of the library map file. The default is cds.lib. This parameter is optional.

-family family_name

This option specifies the target library, for example xce4000x. Use the xce4000x library to target designs implemented in the XC4000EX/XL/XV device architectures.

-gcmd filename

The -gcmd filename option specifies the name of the command file, if any. The default is global.cmd. This parameter is optional.

-help

This option prints a usage message allowing you to obtain more information on CONCEPT2XIL and its options. This parameter is optional.

-log filename

This option specifies the name of the log file. The default is concept2xil.log. This parameter is optional.

-rundir dir_name

The -rundir dirname option specifies the name of the director where CONCEPT2XIL runs. The default is xilinx.run. This parameter is optional.

-sim_only

This option generates a Verilog design configuration for Unified library functional simulation only and does not generate EDIF.

Files

This subsection describes CONCEPT2XIL input and output files.

Input Files

The input files are the structural Verilog netlist (V) files generated by the HDL Direct option in Concept when each design block is saved.

Output Files

There are three output files from CONCEPT2XIL.

• Verilog (V) file
  
  This Verilog file defines the following modules.
  
  alias_bit - defines a module used if you rename nets tapped off a bus, usually in conjunction with a TAP, SLICE or MERGE body. The Xilinx Development System EDIF netlister does not support alias bits. If you rename a net (for instance when you tap a bit off a bus and do not keep the same bus name), you must keep the original net name and the new net name separate in your schematic by inserting a buffer component between the new and existing nets.
  
  alias_vector - defines a module used if you rename buses, usually in conjunction with a SLICE or MERGE body. The M1 EDIF netlister does not support alias vectors.
  
  
• Verilog configuration (VF) file
  
  This configuration file contains information about the location of the Verilog netlists for each block of the design.
  
  
• EDIF file
  
  The Xilinx NGDBuild program uses the EDIF file.
  
  CONCEPT2XIL overwrites any existing V and VF files with the same name in the destination directory. Ensure that you do not overwrite any existing files that you want to preserve.
  
  

Error and Warning Messages

This following subsections discuss error and warning messages generated by CONCEPT2XIL.

Error Message

   No acceptable view exists for cell primitive_name in library path_to_library.

If this is the only error message in the log file, ignore it. Any other error messages that display with this message describe the problem.

Error Message

The following error message can display when you run CONCEPT2XIL.

   . . . Architecture not found in your design library

A cell name precedes the message, as shown in the following example.

   Occurrence p1$9p -> calc_lib.synonym.hdl:
   Error! Architecture not found in your design library

The occurrence name (p1$9p) is the value of the PATH property in your Concept schematic. The expansion of the cell name, in terms of the analyzed Verilog, is library.cell.view. The netlister searches for the cell and view in the Concept Unified Schematic library. When the netlister cannot find the cell, it looks in your design library (calc_lib in the example error message).

If you get this type of error message, perform the following steps.

1. Verify that the libraries defined in your cds.lib physically exist in the path given in the cds.lib file.
   
   
2. Verify that the referenced cell exists in the target library and that your cds.lib file defines the cell.
   
   
3. Verify that the cell in the target library has an "hdl" view (subdirectory). If it does not, write the cell to generate this view with HDL Direct enabled. If targeting a Xilinx library, contact Xilinx for a patch.
   
   
4. Verify that the versions of the .sir file in the hdl subdirectory of the library cell and those written to rundir/design_lib/cell/hdl match.
   
   

The .sir files appear as vlog004u.sir, indicating version 004 in this case.

You also receive this error message if you fail to enter the parameter cds_action="ignore" statement in the verilog.v file in the logic/ subdirectory of a LogiBLOX module after generating the symbol for the module. See the “Processing Designs with LogiBLOX Components” appendix for details.

Error Message

The following error message can also display when running CONCEPT2XIL.

   Initializing environment ...
   Error! Cell name not specified

You can find this error message in the CONCEPT2XIL.log file, as shown in the following example.

concept2xil -family xce4000x mydesign

In this example, the error message displays if mydesign is not present in the current working directory or if mydesign is not an entry in design.wrk (the work file specified by the global.cmd file).

CPLD

The CPLD command invokes the CPLD design implementation software (the Fitter). Run the CPLD command in a UNIX command window. Set your current working directory to the project directory which contains your design source netlist files before invoking cpld. For a complete description, see the “Fitter Command and Option Summary” appendix in the CPLD Schematic Design Guide.

DSGNMGR

This command invokes the Xilinx Design Manager, Xilinx's design implementation interface. DSGNMGR syntax can take the following three forms.

dsgnmgr

dsgnmgr project

dsgnmgr -design design.edif

When you use the first form of the command, Design Manager appears with no project loaded. In this context, a project means a Xilinx project.

When you use the second form of the command, the Design Manager appears but with the specified project loaded or opened. The project, a fully specified file name with a .prj extension, is created by Design Manager and contains the project information for a Xilinx project.

When you use the third form of the command, Design Manager finds the specified design file. A design in this context is a netlist file such as an EDIF file. If the design does not already have a Xilinx project associated with it, Design Manager creates a project and appears with this project loaded. If the design does already have a Xilinx project associated with it, Design Manager appears with that project loaded.

For a complete description, see the “Getting Started” chapter in the Design Manager/Flow Engine Reference/User Guide.

LBGUI

This command invokes the LogiBLOX Graphical User Interface.

NGDAnno

The NGDAnno program distributes delays, setup and hold times, and pulse widths found in the physical NCD design file onto the logical design view represented in the NGD file. Physical component locations for PADs combine with the information in the NGD file. For a complete description, see the “NGDAnno” chapter in the Development System Reference Guide.

NGDBuild

The NGDBuild program performs all of the steps necessary to read a netlist file in XNF or EDIF format and create an NGD file describing the logical design (the design in terms of logic elements such as AND gates, OR gates, decoders, and RAMs). The NGD file resulting from an NGDBuild run contains both a logical description of the design reduced to Xilinx NGD (Native Generic Database) primitives and a description in terms of the original hierarchy expressed in the input netlist. The output NGD file maps to the desired device family. For a complete description, see the “NGDBuild” chapter in the Development System Reference Guide.

NGD2VER

The NGD2VER program translates your design into a Verilog HDL file containing a netlist description of the design in terms of Xilinx simulation primitives. Use the Verilog file to perform a simulation with the Verilog-XL Cadence simulator. For functional simulation and post-map timing simulation, you must use NGD2VER with the -tf and -ul options to create the appropriate files for use with the Cadence Verilog-XL simulator. Use NG2VER to perform post-NGDBuild functional simulation, post-Map timing simulation, and post-route timing simulation. For post-implementation simulation, you must also use the -pf option to create a PIN file if you wish to integrate your design into a Concept board level simulation.

Syntax

For post-NGDBuild functional simulation, use the following syntax.

ngd2ver -tf -ul infile.ngd outfile.v

For post-map timing simulation, use the following syntax.

ngd2ver -tf -ul infile.nga outfile.v

For post-implementation timing simulation, use the following syntax.

ngd2ver -tf -ul -pf infile.nga outfile.v

Options

This subsection describes the NGD2VER options.

-tf

The -tf option generates a test fixture file. The file, a ready-to-use template test fixture Verilog file based on the input NGD or NGA file, has a .tv extension. For examples of testbench files, see the annotated templates in the “Files” appendix.

-ul

The -ul option causes NGD2VER to write a Cadence `uselib directive pointing to the appropriate Verilog simulation library into the output Verilog file. NGD2VER writes the path as follows.

`uselib dir=$XILINX/verilog/src/simprims libext=.vmd

$XILINX is the location of the Xilinx software.

Use this option if you are using the Cadence Verilog-XL simulator. If you do not enter a -ul option, the `uselib line does not write into the Verilog file.

Alternatively, specify the path to your simulation library on the Verilog command line with the -y option.

-pf

The -pf option writes out a PIN file, a Cadence signal-to-pin mapping file required by XIL2CDS. NGD2VER generates a PIN file if the input file contains routed external pins and you specified a -pf command line option. The file has a .pin extension.

Files

This subsection describes NGD2VER input and output files.

Input Files

NGD2VER accepts either of the following files as input.

• NGA - a back-annotated logical design file containing Xilinx simulation primitives. If you enter a file name with no extension, NGD2VER looks for a file with an .nga extension and the name you specified. Post-map or post-implementation timing simulation require NGA files as input.
  
  
• NGD - a logical design file containing Xilinx simulation primitives. SIMPRIM-based functional simulation requires an NGD file as input.
  
  

Output Files

Output from NGD2VER consists of the following files.

• Verilog file - a structural Verilog netlist containing the netlist information obtained from the input NGD or NGA file.
  
  
• SDF file - a Standard Delay Format file containing delays obtained from the input file. NGD2VER only generates an SDF file if the input is an NGA file which contains timing information. The SDF file generated by NGD2VER is based on SDF version 2.1.
  
  The SDF file produced is intended solely for use with the Verilog file generated along with it by NGD2VER.
  
  
• TV file - a testbench template file created if you enter the -tf option on the NGD2VER command line. Use this option when using NGD2VER with the Xilinx/Cadence interface.
  
  
• PIN file - a Cadence signal-to-pin mapping file. NGD2VER generates a PIN file if the input file contains routed external pins and you have specified a -pf command line option.
  
  

All output files have the same root name as the NGD or NGA file unless you specify otherwise.

PAR

PAR takes an NCD file, places and routes the design, and outputs an NCD file used by the bitstream generator (BitGen). For a complete description, see the “PAR - Place and Route” chapter in the Development System Reference Guide.

VERILOG

This command invokes the Verilog-XL simulator to perform functional and timing simulation. For a complete description of this command, see the Cadence manual, Verilog-XL User Guide.

Syntax

The syntax varies depending on which simulation you run.

For Unified Library based functional simulation, use the following syntax.

verilog +delay_mode_unit \
design.stim full_path_to_design.v \
-f full_path_to_design.vf

For SIMPRIM-based functional simulation, use the following syntax.

verilog +delay_mode_unit designf.stim full_path_to_designf.v

For timing simulation, use the following syntax.

verilog full_path_to_designt.stim full_path_to_designt.v

(The “\”at the end of a line indicates that you type the line following the current one on the same command line.)

Options

This subsection describes the Verilog command options.

+delay_mode_unit

Xilinx recommends that you specify the +delay_mode_unit option when performing a functional simulation to specify all delays as unit delays in your simulation. Specifying this option prevents race conditions if any feedback loops exist in your design. Do not use this option for timing simulations.

-f full_path_to_verilog_configuration_file

The -f option reads the Verilog configuration file (VF). Use this option only for Unified Library based functional simulation.

-y full_path_to_library_name

The -y option requires the full path name to the directory of the simulation library you want to use. You must specify the +libtext+ extension also when you use the -y option. This extension specifies a library in the simulation library module. If you need to explicitly specify the SIMPRM Verilog library modules, use the .vmd extension. This option is not required.

+libtext+

This option selects the library file extensions. For the functional and timing simulations described in this manual, this option is either.v or .vmd.

Files

This subsection describes Verilog-XL input and output files.

Input Files

Input files include the following files for these simulations.

• Verilog (V) file - Unified Library based functional simulation requires this file. The file, generated using the -sim_only option with CONCEPT2XIL, defines the following modules.
  
  alias_bit - defines a module used if you rename nets tapped off a bus, usually in conjunction with a TAP, SLICE or MERGE body. The M1 EDIF netlister does not support alias bits. If you rename a net (for instance when you tap a bit off a bus and do not keep the same bus name), you must keep the original net name and the new net name separate in your schematic by inserting a buffer component between the new and existing nets.
  
  alias_vector - defines a module used if you rename buses, usually in conjunction with a SLICE or MERGE body. The M1 EDIF netlister does not support alias vectors.
  
  
• Verilog configuration file - the configuration file, design.vf, contains information about the location of the Verilog netlist for each block of the design. The -sim_only option of the CONCEPT2XIL command generates this file, used when conducting Unified Library based functional simulation in conjunction with HDL Direct.
  
  
• Testbench file (TV) - a user-specified test fixture file that you can create from a testbench template. Functional and timing simulations use a copy of the testbench file (STIM).
  
  

• A structural Verilog HDL file containing the netlist information obtained from the input NGA file. NGD2VER generates this file, used in SIMPRIM-based functional simulation, post-map timing simulation, and post-implementation timing simulation.
  
  
• Testbench file (TV) - a user-specified test fixture file that you can create from the testbench template generated from NGD2VER. Functional and timing simulations use a copy of the testbench file (STIM).
  
  

• A structural Verilog HDL file containing the netlist information obtained from the input NGA file. NGD2VER generates this file, used in SIMPRIM-based functional simulation, post-map timing simulation, and post-implementation timing simulation.
  
  
• SDF file - a Standard Delay Format file containing the delays for the design, required for timing simulation only. NGD2VER automatically writes a directive, $sdf_annotate, to your Verilog netlist specifying the appropriate .sdf file to use in conjunction with that netlist. The SDF file is based on SDF version 2.1.
  
  The SDF file is intended solely for use with the Verilog file generated along with it by NGD2VER.
  
  
• Testbench file (TV) - a user-specified test fixture file that you can create from the testbench template generated from NGD2VER. Functional and timing simulations use a copy of the testbench file (STIM).
  
  

Output File

The output file name is verilog.log. Verilog-XL writes a record of all simulation commands and outputs associated with the $display and $monitor commands specified in your test fixture file. Any error or warning messages issued by Verilog-XL also write to the log.

XIL2CDS

XIL2CDS, a Cadence-supported utility, integrates a Xilinx FPGA or CPLD into a board level schematic for board level simulation and routing. The command generates a symbol body for the FPGA/CPLD you can instantiate into a board level schematic, and a chips_prt file that used to document information about the FPGA/CPLD. For a complete description of this command, contact Cadence Design Systems.

Ensure that you use the current, updated version of the Xilinx .PIN file for ball grid and pin grid arrays. Copy the latest version as follows.

cp $XILINX/cadence/data/xilinx.pga.pin \
$CDS_INST_DIR/share/libary/xilinx/data/ \
xilinx.pga.pin

Syntax

The following syntax illustrates how to create the chips_prt and body output files.

xil2cds verilog_filename -family architecture -mode mode_type -pkg pkg_type -lwbverilog

Options

This section describes the main XIL2CDS options.

-family architecture

This option instructs XIL2CDS to use the package and pin files for the family specified by the architecture name. Use this option for block mode designs that do not have a PART property specifying the target device.

The valid architecture values are 3000, 4000E, 4000X (including Xilinx XC4000EX/XL/XV), 5200, and 9000. For example, enter “4000X” for the XC4000XL. The 4000L architecture is part of the 4000E architecture.

-mode mode_type

This option specifies the type of package pins to include in the output files. You can use the following values.

pkg - Include only the user pins and programming pins.

sp - Include user, programming and special mode pins.

all - Include all pins.

user - Include only user pins.

The default is pkg.

-pkg pkg_file

This option specifies which package file XIL2CDS uses. The default uses the package file corresponding to the target device you have specified. Package files reside in the $XILINX/cadence/data directory.

-lwbverilog

This option creates the output files, chips_prt and body.1.1 for the FPGA or CPLD.

Files

This subsection describes XIL2CDS input and output files.

Input Files

Use the following as input files for the XIL2CDS command.

• Routed Verilog netlist - the V file generated by NGD2VER
  
  
• Cadence XIL2CDS package file - this file contains data used to create a body. The package files reside in the $XILINX/cadence/data directory
  
  
• PIN files - a Cadence signal-to-pin mapping file generated by NGD2VER.
  
  
• SDF file - Standard Delay Format file containing the design delay data.
  
  

Output Files

Use the following as output files for the XIL2CDS command.

• chips_prt - the physical part file for the Xilinx device
  
  
• Body - the symbolic representation of the Xilinx device