Files

The following files assist in the processing of a design through the Cadence interface.

• CONCEPT2XIL creates a .edf file, an EDIF netlist file.
  
  
• EDIF2NGD creates an NGO file, which contains netlist information in a proprietary data base format. The NGO file is a binary file.
  
  
• A User Constraints File (UCF), an input file to NGDBuild, contains user-specified constraints for the map, place, and route tools. This file contains I/O locations and maximum timing delays.
  
  
• NGDBuild creates an NGD file containing a gate-level logical description of the design.
  
  
• MAP or PAR create a native circuit design (NCD) file containing a physical description of the design.
  
  
• NGDAnno creates an NGA file containing physical timing delay information.
  
  
• NGD2VER creates V, TV, PIN, and SDF files if the input file is an NGA file when invoked with the -tf and -pf options. The SDF file contains delay information.
  
  The -tf option creates a Verilog test bench or stimulus file template (TV file).
  
  The -pf option creates a PIN file which contains pinout information for a design. You cannot use the -pf option if the input to NGD2VER is an NGD file. The PIN file correlates each signal in the design to a pin on a particular Xilinx FPGA package.
  
  Running NGD2VER with an NGA file input always creates V and SDF files.
  
  
• A PKG file defines the pins on a Xilinx FPGA or CPLD package. These files, supplied by Xilinx, reside in $XILINX/cadence/data.