Design Approaches

You can enter a design using schematics or a hardware description language (HDL) such as Verilog.

Schematic Entry

This general procedure describes the schematic entry flow.

1. Enter your design using the Concept schematic editor.
   
   

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   NOTE

   You must have Concept's HDL Direct mode enabled. For details, see the “Getting Started” chapter. With HDL Direct enabled, Concept generates a Verilog netlist automatically when you save a drawing.

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2. Process the Verilog files that Concept produces with the CONCEPT2XIL netlister using the -sim_only command line option.
   
   
3. Functionally simulate your design using Verilog-XL.
   
   
4. Translate your design into EDIF format using CONCEPT2XIL.
   
   
5. Use NGDBuild in the Xilinx Design Manager or the command line tool to convert the EDIF file to an NGD file.
   
   
6. Implement your design with the Xilinx Design Manager/Flow Engine. (You can also use the command line versions of these programs.)
   
   If you perform a manual translation of your design, you can also conduct a post-MAP simulation to obtain a rough timing simulation before adding routing delays. Alternatively, you can run TRCE after mapping to evaluate timing before adding net delays. For an explanation of TRCE, see the “TRACE” chapter in the Development System Reference Guide.
   
   
7. Perform timing simulation on the design using Verilog-XL and a test bench stimulus file.
   
   
8. Download your design to the FPGA, or program the CPLD.
   
   
9. Optionally, use the XIL2CDS program to integrate your chip-level design into a board level schematic.
   
   

Mixed-Mode Entry, Top Level Schematic

1. Capture the top level schematic in Concept.
   
   
2. Make sure that each non-schematic block processes to either an NGO, XNF, or EDIF format file. If you have HDL blocks, synthesize these first, then translate them to one of the previous three formats.
   
   
3. Generate a Concept body for each non-schematic block, either manually, or using the genview utility in Concept.
   
   
4. Instantiate the body into the appropriate sheet (page) of your schematic design.
   
   
5. Save your design. (You must have Concept's HDL Direct mode enabled; for details, see the “Getting Started” chapter.)
   
   
6. Add the following line after the part list in your Verilog netlist.
   
   parameter cds_action=”ignore”;
   
   
7. Translate your design into EDIF format using CONCEPT2XIL.
   
   
8. Use NGDBuild in the Xilinx Design Manager or the command line tool to convert the EDIF file to an NGD file and merge the NGO files with the rest of the design.
   
   
9. Optionally, generate an unrouted post-NGDBuild Verilog netlist using NGD2VER and perform a SIMPRIM-based functional simulation.
   
   If you conduct a manual translation, you can also perform a functional simulation to obtain a rough estimate of delays in the unrouted design.
   
   
10. Implement your design with the Xilinx Design Manager/Flow Engine, or perform these steps manually if you prefer.
    
    If you perform a manual translation, you can also perform a post-Map simulation to get an approximate estimate of delays in the unrouted design.
    
    
11. Place and route (PAR) and conduct a back-annotation (NGDAnno) on your design before performing timing simulation.
    
    
12. Perform timing simulation on the design using Verilog-XL and a test bench stimulus file.
    
    
13. Download your design to the FPGA, or program the CPLD.
    
    
14. Optionally, use the XIL2CDS program to integrate your chip-level design into a board level schematic.