Requirements For HDL Direct Compliance

The Xilinx/Cadence schematic design flow requires that you convert SCALD schematic designs to HDL Direct compliant.

Your SCALD schematic drawings must adhere to the following rules.

• Replace SCALD BIT TAP symbols with the HDL Direct SLICE symbols.
  
  
• Use HDL Direct TAP symbols in place of SCALD LSB TAP and MSB TAP symbols.
  
  
• Attach HDL Direct port symbols from hdl_direct_lib to the signals in a schematic which correspond to pins on a symbol body at an upper-level of hierarchy in the design instead of the SCALD convention of attaching an “\I” suffix to interface signals. Attach INPORTS to the inputs, OUTPORTS to the outputs, and IOPORTS to the bidirectional signals of the schematic.
  
  
• Replace SIGN EXTEND and SLASH symbols with the equivalent wiring.
  
  
• Remove the “\I” from all signal names.
  
  
• Remove FLAG symbols from schematics.
  
  
• Remove the \G and place a forward slash (/) at the beginning of the signal for signals that end with \G (which designates them as global signals).
  
  
• Do not connect wires or signals to pass-thru pins on pads. Connect them only to the main pin. Use the “bubble_check off” option with the SCALD compiler.
  
  
• Replace NOT bodies with wires.
  
  
• Rename all signals and symbol names starting with numbers to valid Verilog identifiers. For example, replace 1MYSIGNAL with MYSIGNAL1.
  
  
• Use the GND and VCC symbols from the appropriate Xilinx architecture library because SUPPLY_0 and SUPPLY_1 are not supported.
  
  
• Replace the SCALD signal concatenation operator colon (:) with the HDL Direct signal concatenation operator ampersand (&).
  
  
• Replace the signal replication operator “\R number” and the REPLICATE symbol with a concatenation of the required number of signals. Replace the SCALD REPLICATE symbol in the same way.
  
  
• Replace the SCALD SYNONYM symbols with the HDL Direct ALIAS symbols; however, Xilinx does not support ALIAS symbols.
  
  
• Do not give signals and bodies the same name; they cannot share the same name.
  
  
• Use Verilog naming rules on property values.
  
  

For more detailed and up-to-date information, refer to the “Converting SCALD Schematics into HDL Direct Schematics” of the “Using HDL Direct With SCALD Applications” chapter of the Cadence manual, HDL Direct User Guide.