To conform to naming restrictions in Concept and to prevent overlap with built-in Verilog primitives, use the Xilinx library components and naming conventions in the Concept and Verilog Unified libraries, as shown in the following table.
| Xilinx Component Name | Cadence Component Name | Component Description | Applicable Families |
|---|---|---|---|
| BUF | BUFF | General purpose non-inverting buffer | XC3000 XC4000E/L XC4000EX/XL/XV XC5200 XC9000/XL Spartan/XL |
| PULLDOWN | PULLDOWN1 | Resistor to GND for input PADs | XC4000E/L XC4000EX/XL/XV XC5200 Spartan/XL |
| PULLUP | PULLUP1 | Resistor to VCC for input PADs, open-drain, and tristate outputs | XC3000 XC4000E/L XC4000EX/XL/XV XC5200 XC9000/XL Spartan/XL |
A translation table located at $XILINX/cadence/data/cadence.ttl maps the Concept component names to the Xilinx component names for these library components.
In addition, several of the component names changed in the new M1 Xilinx Concept Unified Libraries for consistency with the Xilinx Unified Library conventions. The following table summarizes these name changes.
| Old Name | New Name |
|---|---|
| ILD1 | ILD_1 |
| ILDI1 | ILDI_1 |
| ILDX1 | ILDX_1 |
| ILDXI1 | ILDXI_1 |
